FPGC_tb.v 7.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322
  1. /*
  2. * Testbench
  3. * Simulates the entire FPGC
  4. */
  5. // Set timescale
  6. `timescale 1 ns/1 ns
  7. // tld
  8. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/FPGC6.v"
  9. // other logic
  10. `include "/home/bart/Documents/FPGA/FPGC5/Verilog/modules/MultiStabilizer.v"
  11. `include "/home/bart/Documents/FPGA/FPGC5/Verilog/modules/DtrReset.v"
  12. // cpu
  13. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/CPU.v"
  14. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/ALU.v"
  15. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/ControlUnit.v"
  16. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/InstructionDecoder.v"
  17. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/Regbank.v"
  18. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/Stack.v"
  19. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/InstrMem.v"
  20. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/DataMem.v"
  21. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/Regr.v"
  22. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/Arbiter.v"
  23. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/IntController.v"
  24. // memory
  25. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/Memory/VRAM.v"
  26. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/Memory/mt48lc16m16a2.v"
  27. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/Memory/w25q128jv.v"
  28. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/Memory/SDRAMcontroller.v"
  29. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/Memory/SPIreader.v"
  30. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/Memory/ROM.v"
  31. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/Memory/MemoryUnit.v"
  32. // io
  33. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/IO/Keyboard.v"
  34. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/IO/OStimer.v"
  35. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/IO/UARTtx.v"
  36. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/IO/UARTrx.v"
  37. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/IO/SimpleSPI.v"
  38. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/IO/LEDvisualizer.v"
  39. // gpu
  40. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/FSX.v"
  41. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/BGWrenderer.v"
  42. //`include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/Spriterenderer.v"
  43. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/TimingGenerator.v"
  44. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/HDMI/RGB2HDMI.v"
  45. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/HDMI/TMDSenc.v"
  46. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/HDMI/lvds.v"
  47. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/HDMI/ddr.v"
  48. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/NTSC/NTSC.v"
  49. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/NTSC/PhaseGen.v"
  50. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/NTSC/RGB332toNTSC.v"
  51. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/NTSC/RGBtoYPhaseAmpl.v"
  52. // Define testmodule
  53. module FPGC_tb;
  54. //Clock I/O
  55. reg clk;
  56. reg clk_SDRAM;
  57. reg nreset;
  58. //SPI0 Flash
  59. wire SPI0_clk;
  60. wire SPI0_cs;
  61. wire SPI0_data;
  62. wire SPI0_wp;
  63. wire SPI0_q;
  64. wire SPI0_hold;
  65. W25Q128JV spiFlash (
  66. .CLK (SPI0_clk),
  67. .DIO (SPI0_data),
  68. .CSn (SPI0_cs),
  69. .WPn (SPI0_wp),
  70. .HOLDn (SPI0_hold),
  71. .DO (SPI0_q)
  72. );
  73. //SDRAM
  74. wire SDRAM_CLK; // SDRAM clock
  75. wire [15 : 0] SDRAM_DQ; // SDRAM I/O
  76. wire [12 : 0] SDRAM_A; // SDRAM Address
  77. wire [1 : 0] SDRAM_BA; // Bank Address
  78. wire SDRAM_CKE; // Synchronous Clock Enable
  79. wire SDRAM_CSn; // CS#
  80. wire SDRAM_RASn; // RAS#
  81. wire SDRAM_CASn; // CAS#
  82. wire SDRAM_WEn; // WE#
  83. wire [1 : 0] SDRAM_DQM; // Mask
  84. mt48lc16m16a2 sdram (
  85. .Dq (SDRAM_DQ),
  86. .Addr (SDRAM_A),
  87. .Ba (SDRAM_BA),
  88. .Clk (SDRAM_CLK),
  89. .Cke (SDRAM_CKE),
  90. .Cs_n (SDRAM_CSn),
  91. .Ras_n (SDRAM_RASn),
  92. .Cas_n (SDRAM_CASn),
  93. .We_n (SDRAM_WEn),
  94. .Dqm (SDRAM_DQM)
  95. );
  96. //HDMI
  97. wire [3:0] TMDS_p;
  98. wire [3:0] TMDS_n;
  99. //SPI1
  100. wire SPI1_clk;
  101. wire SPI1_cs;
  102. wire SPI1_mosi;
  103. wire SPI1_miso;
  104. wire SPI1_rst;
  105. reg SPI1_nint;
  106. //SPI2
  107. wire SPI2_clk;
  108. wire SPI2_cs;
  109. wire SPI2_mosi;
  110. wire SPI2_miso;
  111. wire SPI2_rst;
  112. reg SPI2_nint;
  113. //SPI3
  114. wire SPI3_clk;
  115. wire SPI3_cs;
  116. wire SPI3_mosi;
  117. wire SPI3_miso;
  118. wire SPI3_nrst;
  119. reg SPI3_int;
  120. //SPI4
  121. wire SPI4_clk;
  122. wire SPI4_cs;
  123. wire SPI4_mosi;
  124. wire SPI4_miso;
  125. reg SPI4_gp;
  126. //UART0
  127. reg UART0_in;
  128. wire UART0_out;
  129. reg UART0_dtr;
  130. //UART1
  131. //reg UART1_in;
  132. //wire UART1_out;
  133. //UART2
  134. reg UART2_in;
  135. wire UART2_out;
  136. //PS/2
  137. reg PS2_clk;
  138. reg PS2_data;
  139. //Led
  140. wire led;
  141. //GPIO
  142. wire [3:0] GPO;
  143. reg [3:0] GPI;
  144. //DIP Switch
  145. reg [3:0] DIPS;
  146. FPGC6 fpgc (
  147. .clk(clk),
  148. .clk_SDRAM(clk_SDRAM),
  149. .nreset(nreset),
  150. //HDMI
  151. .TMDS_p(TMDS_p),
  152. .TMDS_n(TMDS_n),
  153. //SDRAM
  154. .SDRAM_CLK(SDRAM_CLK),
  155. .SDRAM_CSn(SDRAM_CSn),
  156. .SDRAM_WEn(SDRAM_WEn),
  157. .SDRAM_CASn(SDRAM_CASn),
  158. .SDRAM_RASn(SDRAM_RASn),
  159. .SDRAM_CKE(SDRAM_CKE),
  160. .SDRAM_A(SDRAM_A),
  161. .SDRAM_BA(SDRAM_BA),
  162. .SDRAM_DQM(SDRAM_DQM),
  163. .SDRAM_DQ(SDRAM_DQ),
  164. //SPI0 flash
  165. .SPI0_clk(SPI0_clk),
  166. .SPI0_cs(SPI0_cs),
  167. .SPI0_data(SPI0_data),
  168. .SPI0_q(SPI0_q),
  169. .SPI0_wp(SPI0_wp),
  170. .SPI0_hold(SPI0_hold),
  171. //SPI1 CH376 bottom
  172. .SPI1_clk(SPI1_clk),
  173. .SPI1_cs(SPI1_cs),
  174. .SPI1_mosi(SPI1_mosi),
  175. .SPI1_miso(SPI1_miso),
  176. .SPI1_nint(SPI1_nint),
  177. .SPI1_rst(SPI1_rst),
  178. //SPI2 CH376 top
  179. .SPI2_clk(SPI2_clk),
  180. .SPI2_cs(SPI2_cs),
  181. .SPI2_mosi(SPI2_mosi),
  182. .SPI2_miso(SPI2_miso),
  183. .SPI2_nint(SPI2_nint),
  184. .SPI2_rst(SPI2_rst),
  185. //SPI3 W5500
  186. .SPI3_clk(SPI3_clk),
  187. .SPI3_cs(SPI3_cs),
  188. .SPI3_mosi(SPI3_mosi),
  189. .SPI3_miso(SPI3_miso),
  190. .SPI3_int(SPI3_int),
  191. .SPI3_nrst(SPI3_nrst),
  192. //SPI4 GP
  193. .SPI4_clk(SPI4_clk),
  194. .SPI4_cs(SPI4_cs),
  195. .SPI4_mosi(SPI4_mosi),
  196. .SPI4_miso(SPI4_miso),
  197. .SPI4_gp(SPI4_gp),
  198. //UART0
  199. .UART0_in(UART0_in),
  200. .UART0_out(UART0_out),
  201. .UART0_dtr(UART0_dtr),
  202. //UART1
  203. //.UART1_in(UART1_in),
  204. //.UART1_out(UART1_out),
  205. //UART2
  206. .UART2_in(UART2_in),
  207. .UART2_out(UART2_out),
  208. //PS/2
  209. .PS2_clk(PS2_clk),
  210. .PS2_data(PS2_data),
  211. //Led for debugging
  212. .led(led),
  213. //GPIO
  214. .GPI(GPI),
  215. .GPO(GPO),
  216. //DIP switch
  217. .DIPS(DIPS)
  218. );
  219. initial
  220. begin
  221. //Dump everything for GTKwave
  222. $dumpfile("/home/bart/Documents/FPGA/FPGC6/Verilog/output/wave.vcd");
  223. $dumpvars;
  224. clk = 0;
  225. clk_SDRAM = 0;
  226. nreset = 1;
  227. SPI1_nint = 1;
  228. SPI2_nint = 1;
  229. SPI3_int = 0;
  230. SPI4_gp = 1;
  231. UART0_in = 1;
  232. UART0_dtr = 1;
  233. //UART1_in = 1;
  234. UART2_in = 1;
  235. PS2_clk = 1;
  236. PS2_data = 0;
  237. GPI = 4'b1111;
  238. DIPS = 4'b0001;
  239. repeat(10)
  240. begin
  241. #5 clk_SDRAM = ~clk_SDRAM; clk = ~clk; //50MHz
  242. #5 clk_SDRAM = ~clk_SDRAM; //100MHz
  243. end
  244. nreset = 0;
  245. repeat(10)
  246. begin
  247. #5 clk_SDRAM = ~clk_SDRAM; clk = ~clk; //50MHz
  248. #5 clk_SDRAM = ~clk_SDRAM; //100MHz
  249. end
  250. nreset = 1;
  251. repeat(40000)
  252. begin
  253. #5 clk_SDRAM = ~clk_SDRAM; clk = ~clk; //50MHz
  254. #5 clk_SDRAM = ~clk_SDRAM; //100MHz
  255. end
  256. repeat(1000)
  257. begin
  258. #5 clk_SDRAM = ~clk_SDRAM; clk = ~clk; //50MHz
  259. #5 clk_SDRAM = ~clk_SDRAM; //100MHz
  260. end
  261. #1 $finish;
  262. end
  263. endmodule