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bart
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FPGC6
réplica de https://github.com/bartpleiter/FPGC6
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Rama: EP4CE15
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FPGC6
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Verilog
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bart 9f74a9565f Fixed more MU I/O bugs. Updated everything from BCC except the ASM to work on new CPU. Added back flasher programs. Fixed LOAD/HI bug by using unsigned const16 instead. Updated assembler including hotfix for FPGC jumping to addr3 after UART bootloader is done. FPGC6 now basically fully works again! %!s(int64=2) %!d(string=hai) anos
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B32P.gtkw 69e83fb855 Fully implemented interrupts in verilog. Return address appears to work fine, but might need some further testing for different delays in the pipeline. %!s(int64=2) %!d(string=hai) anos
FPGC.gtkw 9f74a9565f Fixed more MU I/O bugs. Updated everything from BCC except the ASM to work on new CPU. Added back flasher programs. Fixed LOAD/HI bug by using unsigned const16 instead. Updated assembler including hotfix for FPGC jumping to addr3 after UART bootloader is done. FPGC6 now basically fully works again! %!s(int64=2) %!d(string=hai) anos