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zrcadlo https://github.com/bartpleiter/FPGC6
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Větev: EP4CE15
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FPGC6
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Verilog
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modules
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GPU
bart 1026f4776c Cleaned up some files před 2 roky
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HDMI b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram před 2 roky
NTSC 1026f4776c Cleaned up some files před 2 roky
BGWrenderer.v b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram před 2 roky
FSX.v b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram před 2 roky
TimingGenerator.v 1026f4776c Cleaned up some files před 2 roky