FPGC6.v 14 KB

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  1. /*
  2. * Top level design of the FPGC6
  3. */
  4. module FPGC6(
  5. input clk, //50MHz
  6. input clk_SDRAM, //100MHz
  7. input nreset,
  8. //HDMI
  9. output wire [3:0] TMDS_p,
  10. output wire [3:0] TMDS_n,
  11. //SDRAM
  12. output SDRAM_CLK,
  13. output SDRAM_CSn,
  14. output SDRAM_WEn,
  15. output SDRAM_CASn,
  16. output SDRAM_RASn,
  17. output SDRAM_CKE,
  18. output [12:0] SDRAM_A,
  19. output [1:0] SDRAM_BA,
  20. output [1:0] SDRAM_DQM,
  21. inout [15:0] SDRAM_DQ,
  22. //SPI0 flash
  23. output SPI0_clk,
  24. output SPI0_cs,
  25. inout SPI0_data,
  26. inout SPI0_q,
  27. inout SPI0_wp,
  28. inout SPI0_hold,
  29. //SPI1 CH376 bottom
  30. output SPI1_clk,
  31. output SPI1_cs,
  32. output SPI1_mosi,
  33. input SPI1_miso,
  34. input SPI1_nint,
  35. output SPI1_rst,
  36. //SPI2 CH376 top
  37. output SPI2_clk,
  38. output SPI2_cs,
  39. output SPI2_mosi,
  40. input SPI2_miso,
  41. input SPI2_nint,
  42. output SPI2_rst,
  43. //SPI3 W5500
  44. output SPI3_clk,
  45. output SPI3_cs,
  46. output SPI3_mosi,
  47. input SPI3_miso,
  48. input SPI3_int,
  49. output SPI3_nrst,
  50. //SPI4 GP
  51. output SPI4_clk,
  52. output SPI4_cs,
  53. output SPI4_mosi,
  54. input SPI4_miso,
  55. input SPI4_gp,
  56. //UART0
  57. input UART0_in,
  58. output UART0_out,
  59. input UART0_dtr,
  60. //UART1 (currently unused because no UART midi synth anymore)
  61. //input UART1_in,
  62. //output UART1_out,
  63. //UART2
  64. input UART2_in,
  65. output UART2_out,
  66. //PS/2
  67. input PS2_clk, PS2_data,
  68. //Led for debugging
  69. output led,
  70. //GPIO
  71. input [3:0] GPI,
  72. output [3:0] GPO,
  73. //DIP switch
  74. input [3:0] DIPS,
  75. //I2S audio
  76. output I2S_SDIN, I2S_SCLK, I2S_LRCLK, I2S_MCLK,
  77. //Status leds
  78. output led_Booted, led_Eth, led_Flash, led_USB0, led_USB1, led_PS2, led_HDMI, led_QSPI, led_GPU, led_I2S
  79. );
  80. // TMP FIXES FOR NEW PCB
  81. assign I2S_SDIN = 1'b0;
  82. assign I2S_SCLK = 1'b0;
  83. assign I2S_LRCLK = 1'b0;
  84. assign I2S_MCLK = 1'b0;
  85. //-------------------CLK-------------------------
  86. //In hardware a PLL should be used here
  87. // to create the clk and crt_clk
  88. //assign crt_clk = clk; //'fix' for simulation
  89. //Run VGA at CRT speed
  90. //assign vga_clk = crt_clk;
  91. wire clkTMDShalf; // TMDS clock (pre-DDR), 5x pixel clock
  92. wire clkPixel; // Pixel clock
  93. wire clk14; // NTSC clock
  94. wire clk114; // NTSC color clock
  95. wire clkMuxOut; // HDMI or NTSC clock, depending on selectOutput
  96. // everything at clk speed for simulation
  97. assign clkTMDShalf = clk;
  98. assign clkPixel = clk;
  99. assign clk14 = clk;
  100. assign clk114 = clk;
  101. assign clkMuxOut = clk;
  102. //Run SDRAM at 100MHz
  103. assign SDRAM_CLK = clk_SDRAM;
  104. //--------------------Reset&Stabilizers-----------------------
  105. //Reset signals
  106. wire nreset_stable, UART0_dtr_stable, reset;
  107. //Dip switch
  108. wire boot_mode_stable;
  109. //GPU: High when frame just rendered (needs to be stabilized)
  110. wire frameDrawn, frameDrawn_stable;
  111. //Stabilized SPI interrupt signals
  112. wire SPI1_nint_stable, SPI2_nint_stable, SPI3_int_stable, SPI4_gp_stable;
  113. MultiStabilizer multistabilizer (
  114. .clk(clk),
  115. .u0(nreset),
  116. .s0(nreset_stable),
  117. .u1(UART0_dtr),
  118. .s1(UART0_dtr_stable),
  119. .u2(SPI1_nint),
  120. .s2(SPI1_nint_stable),
  121. .u3(SPI2_nint),
  122. .s3(SPI2_nint_stable),
  123. .u4(SPI3_int),
  124. .s4(SPI3_int_stable),
  125. .u5(SPI4_gp),
  126. .s5(SPI4_gp_stable),
  127. .u6(frameDrawn),
  128. .s6(frameDrawn_stable),
  129. .u7(DIPS[0]),
  130. .s7(boot_mode_stable)
  131. );
  132. //Indicator for opened Serial port
  133. assign led = UART0_dtr_stable;
  134. //DRT to reset pulse
  135. wire dtrRst;
  136. DtrReset dtrReset (
  137. .clk(clk),
  138. .dtr(UART0_dtr_stable),
  139. .dtrRst(dtrRst)
  140. );
  141. assign reset = (~nreset_stable) || dtrRst;
  142. //External reset outputs
  143. assign SPI1_rst = reset;
  144. assign SPI2_rst = reset;
  145. assign SPI3_nrst = ~reset;
  146. //---------------------------VRAM32---------------------------------
  147. //VRAM32 I/O
  148. wire vram32_gpu_clk;
  149. wire [13:0] vram32_gpu_addr;
  150. wire [31:0] vram32_gpu_d;
  151. wire vram32_gpu_we;
  152. wire [31:0] vram32_gpu_q;
  153. wire vram32_cpu_clk;
  154. wire [13:0] vram32_cpu_addr;
  155. wire [31:0] vram32_cpu_d;
  156. wire vram32_cpu_we;
  157. wire [31:0] vram32_cpu_q;
  158. //because FSX will not write to VRAM
  159. assign vram32_gpu_we = 1'b0;
  160. assign vram32_gpu_d = 32'd0;
  161. VRAM #(
  162. .WIDTH(32),
  163. .WORDS(1056),
  164. .LIST("/home/bart/Documents/FPGA/FPGC6/Verilog/memory/vram32.list")
  165. ) vram32(
  166. //CPU port
  167. .cpu_clk (clk),
  168. .cpu_d (vram32_cpu_d),
  169. .cpu_addr (vram32_cpu_addr),
  170. .cpu_we (vram32_cpu_we),
  171. .cpu_q (vram32_cpu_q),
  172. //GPU port
  173. .gpu_clk (clkMuxOut),
  174. .gpu_d (vram32_gpu_d),
  175. .gpu_addr (vram32_gpu_addr),
  176. .gpu_we (vram32_gpu_we),
  177. .gpu_q (vram32_gpu_q)
  178. );
  179. //---------------------------VRAM322--------------------------------
  180. //VRAM322 I/O
  181. wire vram322_gpu_clk;
  182. wire [13:0] vram322_gpu_addr;
  183. wire [31:0] vram322_gpu_d;
  184. wire vram322_gpu_we;
  185. wire [31:0] vram322_gpu_q;
  186. //because FSX will not write to VRAM
  187. assign vram322_gpu_we = 1'b0;
  188. assign vram322_gpu_d = 32'd0;
  189. VRAM #(
  190. .WIDTH(32),
  191. .WORDS(1056),
  192. .LIST("/home/bart/Documents/FPGA/FPGC6/Verilog/memory/vram32.list")
  193. ) vram322(
  194. //CPU port
  195. .cpu_clk (clk),
  196. .cpu_d (vram32_cpu_d),
  197. .cpu_addr (vram32_cpu_addr),
  198. .cpu_we (vram32_cpu_we),
  199. .cpu_q (),
  200. //GPU port
  201. .gpu_clk (clkMuxOut),
  202. .gpu_d (vram322_gpu_d),
  203. .gpu_addr (vram322_gpu_addr),
  204. .gpu_we (vram322_gpu_we),
  205. .gpu_q (vram322_gpu_q)
  206. );
  207. //--------------------------VRAM8--------------------------------
  208. //VRAM8 I/O
  209. wire vram8_gpu_clk;
  210. wire [13:0] vram8_gpu_addr;
  211. wire [7:0] vram8_gpu_d;
  212. wire vram8_gpu_we;
  213. wire [7:0] vram8_gpu_q;
  214. wire vram8_cpu_clk;
  215. wire [13:0] vram8_cpu_addr;
  216. wire [7:0] vram8_cpu_d;
  217. wire vram8_cpu_we;
  218. wire [7:0] vram8_cpu_q;
  219. //because FSX will not write to VRAM
  220. assign vram8_gpu_we = 1'b0;
  221. assign vram8_gpu_d = 8'd0;
  222. VRAM #(
  223. .WIDTH(8),
  224. .WORDS(8194),
  225. .LIST("/home/bart/Documents/FPGA/FPGC6/Verilog/memory/vram8.list")
  226. ) vram8(
  227. //CPU port
  228. .cpu_clk (clk),
  229. .cpu_d (vram8_cpu_d),
  230. .cpu_addr (vram8_cpu_addr),
  231. .cpu_we (vram8_cpu_we),
  232. .cpu_q (vram8_cpu_q),
  233. //GPU port
  234. .gpu_clk (clkMuxOut),
  235. .gpu_d (vram8_gpu_d),
  236. .gpu_addr (vram8_gpu_addr),
  237. .gpu_we (vram8_gpu_we),
  238. .gpu_q (vram8_gpu_q)
  239. );
  240. //--------------------------VRAMSPR--------------------------------
  241. //VRAMSPR I/O
  242. wire vramSPR_gpu_clk;
  243. wire [13:0] vramSPR_gpu_addr;
  244. wire [8:0] vramSPR_gpu_d;
  245. wire vramSPR_gpu_we;
  246. wire [8:0] vramSPR_gpu_q;
  247. wire vramSPR_cpu_clk;
  248. wire [13:0] vramSPR_cpu_addr;
  249. wire [8:0] vramSPR_cpu_d;
  250. wire vramSPR_cpu_we;
  251. wire [8:0] vramSPR_cpu_q;
  252. //because FSX will not write to VRAM
  253. assign vramSPR_gpu_we = 1'b0;
  254. assign vramSPR_gpu_d = 9'd0;
  255. VRAM #(
  256. .WIDTH(9),
  257. .WORDS(256),
  258. .LIST("/home/bart/Documents/FPGA/FPGC6/Verilog/memory/vramSPR.list")
  259. ) vramSPR(
  260. //CPU port
  261. .cpu_clk (clk),
  262. .cpu_d (vramSPR_cpu_d),
  263. .cpu_addr (vramSPR_cpu_addr),
  264. .cpu_we (vramSPR_cpu_we),
  265. .cpu_q (vramSPR_cpu_q),
  266. //GPU port
  267. .gpu_clk (clkMuxOut),
  268. .gpu_d (vramSPR_gpu_d),
  269. .gpu_addr (vramSPR_gpu_addr),
  270. .gpu_we (vramSPR_gpu_we),
  271. .gpu_q (vramSPR_gpu_q)
  272. );
  273. //-------------------ROM-------------------------
  274. //ROM I/O
  275. wire [8:0] rom_addr;
  276. wire [31:0] rom_q;
  277. ROM rom(
  278. .clk (clk),
  279. .reset (reset),
  280. .address (rom_addr),
  281. .q (rom_q)
  282. );
  283. //-----------------------FSX-------------------------
  284. //FSX I/O
  285. wire [7:0] composite; // NTSC composite video signal
  286. reg selectOutput = 1'b1; // 1 -> HDMI, 0 -> Composite
  287. FSX fsx(
  288. //Clocks
  289. .clkPixel (clkPixel),
  290. .clkTMDShalf (clkTMDShalf),
  291. .clk14 (clk14),
  292. .clk114 (clk114),
  293. .clkMuxOut (clkMuxOut),
  294. //HDMI
  295. .TMDS_p (TMDS_p),
  296. .TMDS_n (TMDS_n),
  297. //NTSC composite
  298. .composite (composite),
  299. //Select output method
  300. .selectOutput (selectOutput),
  301. //VRAM32
  302. .vram32_addr (vram32_gpu_addr),
  303. .vram32_q (vram32_gpu_q),
  304. //VRAM32
  305. .vram322_addr (vram322_gpu_addr),
  306. .vram322_q (vram322_gpu_q),
  307. //VRAM8
  308. .vram8_addr (vram8_gpu_addr),
  309. .vram8_q (vram8_gpu_q),
  310. //VRAMSPR
  311. .vramSPR_addr (vramSPR_gpu_addr),
  312. .vramSPR_q (vramSPR_gpu_q),
  313. //Interrupt signal
  314. .frameDrawn (frameDrawn)
  315. );
  316. //----------------Memory Unit--------------------
  317. //Memory Unit I/O
  318. //Bus
  319. wire [26:0] bus_addr;
  320. wire [31:0] bus_data;
  321. wire bus_we;
  322. wire bus_start;
  323. wire [31:0] bus_q;
  324. wire bus_done;
  325. //Interrupt signals
  326. wire OST1_int, OST2_int, OST3_int;
  327. wire UART0_rx_int, UART2_rx_int;
  328. wire PS2_int;
  329. wire SPI0_QSPI;
  330. MemoryUnit mu(
  331. //clock
  332. .clk (clk),
  333. .clk_SDRAM (clk_SDRAM),
  334. .reset (reset),
  335. //CPU connection (Bus)
  336. .bus_addr (bus_addr),
  337. .bus_data (bus_data),
  338. .bus_we (bus_we),
  339. .bus_start (bus_start),
  340. .bus_q (bus_q),
  341. .bus_done (bus_done),
  342. /********
  343. * MEMORY
  344. ********/
  345. //SPI Flash / SPI0
  346. .SPIflash_data (SPI0_data),
  347. .SPIflash_q (SPI0_q),
  348. .SPIflash_wp (SPI0_wp),
  349. .SPIflash_hold (SPI0_hold),
  350. .SPIflash_cs (SPI0_cs),
  351. .SPIflash_clk (SPI0_clk),
  352. //SDRAM
  353. .SDRAM_CSn (SDRAM_CSn),
  354. .SDRAM_WEn (SDRAM_WEn),
  355. .SDRAM_CASn (SDRAM_CASn),
  356. .SDRAM_CKE (SDRAM_CKE),
  357. .SDRAM_RASn (SDRAM_RASn),
  358. .SDRAM_A (SDRAM_A),
  359. .SDRAM_BA (SDRAM_BA),
  360. .SDRAM_DQM (SDRAM_DQM),
  361. .SDRAM_DQ (SDRAM_DQ),
  362. //VRAM32 cpu port
  363. .VRAM32_cpu_d (vram32_cpu_d),
  364. .VRAM32_cpu_addr (vram32_cpu_addr),
  365. .VRAM32_cpu_we (vram32_cpu_we),
  366. .VRAM32_cpu_q (vram32_cpu_q),
  367. //VRAM8 cpu port
  368. .VRAM8_cpu_d (vram8_cpu_d),
  369. .VRAM8_cpu_addr (vram8_cpu_addr),
  370. .VRAM8_cpu_we (vram8_cpu_we),
  371. .VRAM8_cpu_q (vram8_cpu_q),
  372. //VRAMspr cpu port
  373. .VRAMspr_cpu_d (vramSPR_cpu_d),
  374. .VRAMspr_cpu_addr (vramSPR_cpu_addr),
  375. .VRAMspr_cpu_we (vramSPR_cpu_we),
  376. .VRAMspr_cpu_q (vramSPR_cpu_q),
  377. //ROM
  378. .ROM_addr (rom_addr),
  379. .ROM_q (rom_q),
  380. /********
  381. * I/O
  382. ********/
  383. //UART0 (Main USB)
  384. .UART0_in (UART0_in),
  385. .UART0_out (UART0_out),
  386. .UART0_rx_interrupt (UART0_rx_int),
  387. //UART1 (APU)
  388. /*.UART1_in (),
  389. .UART1_out (),
  390. .UART1_rx_interrupt (),
  391. */
  392. //UART2 (GP)
  393. .UART2_in (UART2_in),
  394. .UART2_out (UART2_out),
  395. .UART2_rx_interrupt (UART2_rx_int),
  396. //SPI0 (Flash)
  397. //declared under MEMORY
  398. .SPI0_QSPI (SPI0_QSPI),
  399. //SPI1 (USB0/CH376T)
  400. .SPI1_clk (SPI1_clk),
  401. .SPI1_cs (SPI1_cs),
  402. .SPI1_mosi (SPI1_mosi),
  403. .SPI1_miso (SPI1_miso),
  404. .SPI1_nint (SPI1_nint_stable),
  405. //SPI2 (USB1/CH376T)
  406. .SPI2_clk (SPI2_clk),
  407. .SPI2_cs (SPI2_cs),
  408. .SPI2_mosi (SPI2_mosi),
  409. .SPI2_miso (SPI2_miso),
  410. .SPI2_nint (SPI2_nint_stable),
  411. //SPI3 (W5500)
  412. .SPI3_clk (SPI3_clk),
  413. .SPI3_cs (SPI3_cs),
  414. .SPI3_mosi (SPI3_mosi),
  415. .SPI3_miso (SPI3_miso),
  416. .SPI3_int (SPI3_int_stable),
  417. //SPI4 (EXT/GP)
  418. .SPI4_clk (SPI4_clk),
  419. .SPI4_cs (SPI4_cs),
  420. .SPI4_mosi (SPI4_mosi),
  421. .SPI4_miso (SPI4_miso),
  422. .SPI4_GP (SPI4_gp_stable),
  423. //GPIO (Separated GPI and GPO until GPIO module is implemented)
  424. .GPI (GPI[3:0]),
  425. .GPO (GPO[3:0]),
  426. //OStimers
  427. .OST1_int (OST1_int),
  428. .OST2_int (OST2_int),
  429. .OST3_int (OST3_int),
  430. //SNESpad
  431. /*
  432. .SNES_clk (),
  433. .SNES_latch (),
  434. .SNES_data (),
  435. */
  436. //PS/2
  437. .PS2_clk (PS2_clk),
  438. .PS2_data (PS2_data),
  439. .PS2_int (PS2_int), //Scan code ready signal
  440. //Boot mode
  441. .boot_mode (boot_mode_stable)
  442. );
  443. //---------------CPU----------------
  444. //CPU I/O
  445. wire [26:0] PC;
  446. CPU cpu(
  447. .clk (clk),
  448. .reset (reset),
  449. // bus
  450. .bus_addr (bus_addr),
  451. .bus_data (bus_data),
  452. .bus_we (bus_we),
  453. .bus_start (bus_start),
  454. .bus_q (bus_q),
  455. .bus_done (bus_done),
  456. .int1 (OST1_int), //OStimer1
  457. .int2 (OST2_int), //OStimer2
  458. .int3 (UART0_rx_int), //UART0 rx (MAIN)
  459. .int4 (frameDrawn_stable), //GPU Frame Drawn
  460. .int5 (OST3_int), //OStimer3
  461. .int6 (PS2_int), //PS/2 scancode ready
  462. .int7 (1'b0), //UART1 rx (APU)
  463. .int8 (UART2_rx_int), //UART2 rx (EXT)
  464. .PC (PC)
  465. );
  466. //-----------STATUS LEDS-----------
  467. assign led_Booted = (PC >= 27'hC02522 | reset);
  468. assign led_HDMI = (~selectOutput | reset);
  469. assign led_QSPI = (~SPI0_QSPI | reset);
  470. LEDvisualizer #(.MIN_CLK(100000))
  471. LEDvisUSB0
  472. (
  473. .clk(clk),
  474. .reset(reset),
  475. .activity(~SPI1_cs),
  476. .LED(led_USB0)
  477. );
  478. LEDvisualizer #(.MIN_CLK(100000))
  479. LEDvisUSB1
  480. (
  481. .clk(clk),
  482. .reset(reset),
  483. .activity(~SPI2_cs),
  484. .LED(led_USB1)
  485. );
  486. LEDvisualizer #(.MIN_CLK(100000))
  487. LEDvisEth
  488. (
  489. .clk(clk),
  490. .reset(reset),
  491. .activity(~SPI3_cs),
  492. .LED(led_Eth)
  493. );
  494. LEDvisualizer #(.MIN_CLK(100000))
  495. LEDvisPS2
  496. (
  497. .clk(clk),
  498. .reset(reset),
  499. .activity(PS2_int),
  500. .LED(led_PS2)
  501. );
  502. LEDvisualizer #(.MIN_CLK(100000))
  503. LEDvisFlash
  504. (
  505. .clk(clk),
  506. .reset(reset),
  507. .activity(~SPI0_cs),
  508. .LED(led_Flash)
  509. );
  510. LEDvisualizer #(.MIN_CLK(100000))
  511. LEDvisGPU
  512. (
  513. .clk(clk),
  514. .reset(reset),
  515. .activity(vram32_cpu_we|vram8_cpu_we|vramSPR_cpu_we),
  516. .LED(led_GPU)
  517. );
  518. LEDvisualizer #(.MIN_CLK(100000))
  519. LEDvisI2S
  520. (
  521. .clk(clk),
  522. .reset(reset),
  523. .activity(I2S_SDIN),
  524. .LED(led_I2S)
  525. );
  526. endmodule