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SDRAMcontroller.v 12 KB

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  1. /*
  2. * SDRAM controller
  3. */
  4. module SDRAMcontroller(
  5. input clk,
  6. // read
  7. output busy, // high if controller is busy
  8. input [23:0] addr, // addr to read or write 2*24 * 16 = 32MiBytes
  9. input [31:0] d, // data to write
  10. input we, // high if write, low if read
  11. input start, // high when controller should start reading/writing
  12. output [31:0] q, // read data output
  13. //output reg q_ready_reg_delay, // read data ready
  14. output q_ready, // read data ready
  15. output initDone, // high when initialization done
  16. // SDRAM
  17. output SDRAM_CSn, SDRAM_WEn, SDRAM_CASn, SDRAM_RASn,
  18. output reg SDRAM_CKE,
  19. output reg [12:0] SDRAM_A,
  20. output reg [1:0] SDRAM_BA,
  21. output reg [1:0] SDRAM_DQM,
  22. inout [15:0] SDRAM_DQ
  23. );
  24. reg q_ready_reg;
  25. assign q_ready = (start && q_ready_reg);
  26. assign busy = (state != s_idle);
  27. assign initDone = (state != s_init);
  28. reg [3:0] SDRAM_CMD;
  29. parameter [3:0] SDRAM_CMD_UNSELECTED= 4'b1000;
  30. parameter [3:0] SDRAM_CMD_NOP = 4'b0111;
  31. parameter [3:0] SDRAM_CMD_ACTIVE = 4'b0011;
  32. parameter [3:0] SDRAM_CMD_READ = 4'b0101;
  33. parameter [3:0] SDRAM_CMD_WRITE = 4'b0100;
  34. parameter [3:0] SDRAM_CMD_TERMINATE = 4'b0110;
  35. parameter [3:0] SDRAM_CMD_PRECHARGE = 4'b0010;
  36. parameter [3:0] SDRAM_CMD_REFRESH = 4'b0001;
  37. parameter [3:0] SDRAM_CMD_LOADMODE = 4'b0000;
  38. assign {SDRAM_CSn, SDRAM_RASn, SDRAM_CASn, SDRAM_WEn} = SDRAM_CMD;
  39. // 48LC16M16A2-7E specs
  40. parameter sdram_column_bits = 10;
  41. parameter sdram_address_width = 25;
  42. parameter sdram_startup_cycles = 10100; // -- 100us, plus a little more, @ 100MHz
  43. parameter cycles_per_refresh = 780; // 25MHz -> 195; // (64000*100)/8192-1 Cycled as (64ms @100MHz)/8192 rows (780 for 100mhz)
  44. // bit indexes used when splitting the address into row/colum/bank.
  45. parameter start_of_col = 0;
  46. parameter end_of_col = sdram_column_bits-2;
  47. parameter start_of_bank = sdram_column_bits-1;
  48. parameter end_of_bank = sdram_column_bits;
  49. parameter START_OF_ROW = sdram_column_bits+1;
  50. parameter END_OF_ROW = sdram_address_width-2;
  51. parameter prefresh_cmd = 10;
  52. parameter ROW_PAD_BITS = 12 + START_OF_ROW - END_OF_ROW;
  53. wire [12:0] addr_row;
  54. wire [12:0] addr_col;
  55. wire [1:0] addr_bank;
  56. //--------------------------------------------------------------------------
  57. // Seperate the address into row / bank / address
  58. //--------------------------------------------------------------------------
  59. //11111111110 111010100
  60. wire [24:0] bigaddr;
  61. assign bigaddr = addr << 1;
  62. assign addr_col = bigaddr[8:0];
  63. assign addr_row = bigaddr[21:9];
  64. assign addr_bank = bigaddr[23:22];
  65. //DQ write port
  66. reg [15:0] WrData;
  67. reg SDRAM_DQ_OE;
  68. assign SDRAM_DQ = SDRAM_DQ_OE ? WrData : 16'hZZZZ;
  69. wire [15:0] SDRAM_Q;
  70. assign SDRAM_Q = SDRAM_DQ;
  71. //Input data
  72. wire [15:0] data_low, data_high;
  73. assign data_low = d[15:0];
  74. assign data_high = d[31:16];
  75. //Output data
  76. reg [15:0] q_low, q_high;
  77. assign q = {q_high, q_low};
  78. // state of controller
  79. reg [6:0] state;
  80. parameter s_init = 0;
  81. parameter s_idle = 1;
  82. parameter s_open_in_2 = 2;
  83. parameter s_open_in_1 = 3;
  84. parameter s_write_1 = 4;
  85. parameter s_write_2 = 5;
  86. parameter s_write_3 = 6;
  87. parameter s_read_1 = 7;
  88. parameter s_read_2 = 8;
  89. parameter s_read_3 = 9;
  90. parameter s_read_4 = 10;
  91. parameter s_precharge = 11;
  92. parameter s_idle_in_6 = 12;
  93. parameter s_idle_in_5 = 13;
  94. parameter s_idle_in_4 = 14;
  95. parameter s_idle_in_3 = 15;
  96. parameter s_idle_in_2 = 16;
  97. parameter s_idle_in_1 = 17;
  98. parameter s_read_precharge = 18;
  99. reg [9:0] startup_refresh_count = 0;
  100. wire refresh;
  101. assign refresh = (SDRAM_CMD == SDRAM_CMD_REFRESH);
  102. //140ns = 1clk
  103. //63980 - 42820 = 21160
  104. // 21160 / 40 = 529 cycles
  105. // 25MHz -> 25.000.000 cycles per sec
  106. // 25.000.000*0.064 -> 1.600.000 cycles per 64ms
  107. // 1.600.000 / 8192 auto refreshes -> refresh after 196 cycles
  108. // for 50mhz this should be 196*2 cycles and for 100mhz this should be 196*4 cycles
  109. reg [31:0] InitCounter = 0;
  110. reg isRefreshing = 1'b0;
  111. always @(posedge clk)
  112. begin
  113. /*if (reset)
  114. begin
  115. SDRAM_BA <= 2'b00;
  116. SDRAM_DQM <= 2'b11;
  117. SDRAM_A <= 0;
  118. SDRAM_CMD <= SDRAM_CMD_UNSELECTED;
  119. SDRAM_CKE <= 0;
  120. SDRAM_DQ_OE <= 0;
  121. state <= 0;
  122. WrData <= 0;
  123. q_ready_reg <= 0;
  124. q_low <= 0;
  125. q_high <= 0;
  126. startup_refresh_count <= 0;
  127. end
  128. else */
  129. begin
  130. startup_refresh_count <= startup_refresh_count+1;
  131. case(state)
  132. s_init:
  133. begin
  134. q_ready_reg <= 1'b0;
  135. SDRAM_CKE <= 1'b1;
  136. SDRAM_DQM <= 2'b00;
  137. case(InitCounter)
  138. 1010: begin
  139. SDRAM_CMD <= SDRAM_CMD_PRECHARGE;
  140. SDRAM_A <= 1024;
  141. end
  142. 1015: begin
  143. SDRAM_CMD <= SDRAM_CMD_REFRESH;
  144. end
  145. 1025: begin
  146. SDRAM_CMD <= SDRAM_CMD_REFRESH;
  147. end
  148. 1035: begin
  149. SDRAM_CMD <= SDRAM_CMD_LOADMODE;
  150. SDRAM_A <= 6'b100001; //cas = 2, and burst length = 2, burst type = sequenctial
  151. end
  152. 1036: begin
  153. SDRAM_CMD <= SDRAM_CMD_NOP;
  154. SDRAM_A <= 0;
  155. state <= s_idle;
  156. end
  157. default: begin
  158. SDRAM_CMD <= SDRAM_CMD_NOP;
  159. end
  160. endcase
  161. InitCounter <= InitCounter + 1'b1;
  162. end
  163. s_idle:
  164. begin
  165. q_ready_reg <= 1'b0;
  166. if (startup_refresh_count > cycles_per_refresh) //refresh has priority!
  167. begin
  168. state <= s_idle_in_6;
  169. isRefreshing <= 1'b1;
  170. SDRAM_CMD <= SDRAM_CMD_REFRESH;
  171. startup_refresh_count <= 0;
  172. end
  173. else
  174. begin
  175. if (start)
  176. begin
  177. //--------------------------------
  178. //-- Start the read or write cycle.
  179. //-- First task is to open the row
  180. //--------------------------------
  181. state <= s_open_in_2;
  182. SDRAM_CMD <= SDRAM_CMD_ACTIVE;
  183. SDRAM_A <= addr_row;
  184. SDRAM_BA <= addr_bank;
  185. end
  186. else //if nothing happens, just nop
  187. begin
  188. SDRAM_DQM <= 2'b00;
  189. SDRAM_CMD <= SDRAM_CMD_NOP;
  190. SDRAM_A <= 0;
  191. end
  192. end
  193. end
  194. s_open_in_2:
  195. begin
  196. state <= s_open_in_1;
  197. SDRAM_CMD <= SDRAM_CMD_NOP;
  198. end
  199. s_open_in_1:
  200. begin
  201. // if write command
  202. if (we)
  203. begin
  204. state <= s_write_1;
  205. WrData <= data_low;
  206. SDRAM_DQ_OE <= 1'b1;
  207. end
  208. else // if read command
  209. begin
  210. state <= s_read_1;
  211. SDRAM_DQ_OE <= 1'b0;
  212. end
  213. end
  214. s_write_1:
  215. begin
  216. state <= s_write_2;
  217. SDRAM_CMD <= SDRAM_CMD_WRITE;
  218. SDRAM_A <= addr_col;
  219. SDRAM_A[prefresh_cmd] <= 1'b0; // A10 actually matters - it selects auto precharge
  220. SDRAM_BA <= addr_bank;
  221. SDRAM_DQM <= 2'b00;
  222. WrData <= data_low;
  223. end
  224. s_write_2:
  225. begin
  226. WrData <= data_high;
  227. SDRAM_CMD <= SDRAM_CMD_NOP;
  228. state <= s_write_3;
  229. end
  230. s_write_3:
  231. begin
  232. state <= s_precharge;
  233. SDRAM_DQ_OE <= 1'b0;
  234. end
  235. s_precharge:
  236. begin
  237. q_ready_reg <= 1'b1;
  238. state <= s_idle_in_3;
  239. SDRAM_CMD <= SDRAM_CMD_PRECHARGE;
  240. SDRAM_A[prefresh_cmd] <= 1'b1; // A10 actually matters - it selects all banks or just one
  241. end
  242. s_idle_in_6:
  243. begin
  244. state <= s_idle_in_5;
  245. SDRAM_CMD <= SDRAM_CMD_NOP;
  246. end
  247. s_idle_in_5: state <= s_idle_in_4;
  248. s_idle_in_4: state <= s_idle_in_3;
  249. s_idle_in_3:
  250. begin
  251. if (!start) q_ready_reg <= 1'b0;
  252. state <= s_idle_in_2;
  253. SDRAM_CMD <= SDRAM_CMD_NOP;
  254. end
  255. s_idle_in_2:
  256. begin
  257. state <= s_idle_in_1;
  258. if (!start) q_ready_reg <= 1'b0;
  259. end
  260. s_idle_in_1:
  261. begin
  262. if (!start || isRefreshing || !q_ready_reg)
  263. begin
  264. q_ready_reg <= 1'b0;
  265. state <= s_idle;
  266. isRefreshing <= 1'b0;
  267. end
  268. end
  269. s_read_1:
  270. begin
  271. state <= s_read_2;
  272. SDRAM_CMD <= SDRAM_CMD_READ;
  273. SDRAM_A <= addr_col;
  274. SDRAM_BA <= addr_bank;
  275. SDRAM_A[prefresh_cmd] <= 1'b0; // A10 actually matters - it selects auto precharge
  276. SDRAM_DQM <= 2'b00;
  277. end
  278. s_read_2: begin
  279. SDRAM_CMD <= SDRAM_CMD_NOP;
  280. state <= s_read_3;
  281. end
  282. s_read_3: begin
  283. state <= s_read_4;
  284. end
  285. s_read_4:
  286. begin
  287. state <= s_read_precharge;
  288. q_low <= SDRAM_Q;
  289. end
  290. s_read_precharge:
  291. begin
  292. q_high <= SDRAM_Q;
  293. q_ready_reg <= 1'b1;
  294. state <= s_idle_in_3;
  295. SDRAM_CMD <= SDRAM_CMD_PRECHARGE;
  296. SDRAM_A[prefresh_cmd] <= 1'b1; // A10 actually matters - it selects all banks or just one
  297. end
  298. endcase
  299. end
  300. end
  301. /*
  302. reg q_ready_reg;
  303. always @(posedge clk)
  304. begin
  305. if (reset)
  306. begin
  307. q_ready_reg_delay <= 0;
  308. end
  309. else
  310. begin
  311. q_ready_reg_delay <= q_ready_reg;
  312. //if (state == s_read_4)
  313. // q_low <= SDRAM_Q;
  314. //if (state == s_read_precharge)
  315. // q_high <= SDRAM_Q;
  316. end
  317. end
  318. */
  319. initial
  320. begin
  321. SDRAM_BA <= 2'b00;
  322. SDRAM_DQM <= 2'b11;
  323. SDRAM_A <= 0;
  324. SDRAM_CMD <= SDRAM_CMD_UNSELECTED;
  325. SDRAM_CKE <= 0;
  326. SDRAM_DQ_OE <= 0;
  327. state <= 0;
  328. WrData <= 0;
  329. q_ready_reg <= 0;
  330. q_low <= 0;
  331. q_high <= 0;
  332. startup_refresh_count <= 0;
  333. //q_ready_reg_delay <= 0;
  334. end
  335. endmodule