Accueil Explorer Aide
Connexion
bart
/
FPGC6
miroir de https://github.com/bartpleiter/FPGC6
1
0
Fork 0
Fichiers Tickets 0 Wiki
Branche: EP4CE15
Branches Tags
FPGC6
/
Quartus
/
clkMux
/
synthesis
bart b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram il y a 2 ans
..
submodules b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram il y a 2 ans
clkMux.debuginfo b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram il y a 2 ans
clkMux.qip b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram il y a 2 ans
clkMux.v b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram il y a 2 ans