FPGC6/Quartus/clkMux/clkMux.xml

<?xml version="1.0" encoding="UTF-8"?>
<deploy
 date="2022.07.04.11:59:14"
 outputDirectory="/home/bart/Documents/FPGA/FPGC5/Quartus/clkMux/">
 <perimeter>
  <parameter
     name="AUTO_GENERATION_ID"
     type="Integer"
     defaultValue="0"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_UNIQUE_ID"
     type="String"
     defaultValue=""
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE_FAMILY"
     type="String"
     defaultValue="Cyclone IV E"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE"
     type="String"
     defaultValue="EP4CE15F23C8"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE_SPEEDGRADE"
     type="String"
     defaultValue="8"
     onHdl="0"
     affectsHdl="1" />
  <interface name="altclkctrl_input" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <port name="inclk1x" direction="input" role="inclk1x" width="1" />
   <port name="inclk0x" direction="input" role="inclk0x" width="1" />
   <port name="clkselect" direction="input" role="clkselect" width="1" />
  </interface>
  <interface name="altclkctrl_output" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <port name="outclk" direction="output" role="outclk" width="1" />
  </interface>
 </perimeter>
 <entity
   path=""
   parameterizationKey="clkMux:1.0:AUTO_DEVICE=EP4CE15F23C8,AUTO_DEVICE_FAMILY=Cyclone IV E,AUTO_DEVICE_SPEEDGRADE=8,AUTO_GENERATION_ID=1656928754,AUTO_UNIQUE_ID=(altclkctrl:21.1:CLOCK_TYPE=1,DEVICE_FAMILY=Cyclone IV E,ENA_REGISTER_MODE=1,GUI_USE_ENA=false,NUMBER_OF_CLOCKS=2,USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION=false)"
   instancePathKey="clkMux"
   kind="clkMux"
   version="1.0"
   name="clkMux">
  <parameter name="AUTO_GENERATION_ID" value="1656928754" />
  <parameter name="AUTO_DEVICE" value="EP4CE15F23C8" />
  <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
  <parameter name="AUTO_UNIQUE_ID" value="" />
  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="8" />
  <generatedFiles>
   <file
       path="/home/bart/Documents/FPGA/FPGC5/Quartus/clkMux/synthesis/clkMux.v"
       type="VERILOG" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/bart/Documents/FPGA/FPGC5/Quartus/clkMux/synthesis/submodules/clkMux_altclkctrl_0.v"
       type="VERILOG"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file path="/home/bart/Documents/FPGA/FPGC5/Quartus/clkMux.qsys" />
  </sourceFiles>
  <childSourceFiles>
   <file
       path="/home/bart/intelFPGA_lite/21.1/ip/altera/megafunctions/altclkctrl/altclkctrl_hw.tcl" />
  </childSourceFiles>
  <messages>
   <message level="Debug" culprit="clkMux">queue size: 0 starting:clkMux "clkMux"</message>
   <message level="Progress" culprit="min"></message>
   <message level="Progress" culprit="max"></message>
   <message level="Progress" culprit="current"></message>
   <message level="Debug">Transform: CustomInstructionTransform</message>
   <message level="Debug">No custom instruction connections, skipping transform </message>
   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>1</b> modules, <b>0</b> connections]]></message>
   <message level="Debug">Transform: MMTransform</message>
   <message level="Debug">Transform: InterruptMapperTransform</message>
   <message level="Debug">Transform: InterruptSyncTransform</message>
   <message level="Debug">Transform: InterruptFanoutTransform</message>
   <message level="Debug">Transform: AvalonStreamingTransform</message>
   <message level="Debug">Transform: ResetAdaptation</message>
   <message level="Debug" culprit="clkMux"><![CDATA["<b>clkMux</b>" reuses <b>altclkctrl</b> "<b>submodules/clkMux_altclkctrl_0</b>"]]></message>
   <message level="Debug" culprit="clkMux">queue size: 0 starting:altclkctrl "submodules/clkMux_altclkctrl_0"</message>
   <message level="Info" culprit="altclkctrl_0">Generating top-level entity clkMux_altclkctrl_0.</message>
   <message level="Debug" culprit="altclkctrl_0">Current quartus bindir: /home/bart/intelFPGA_lite/21.1/quartus/linux64/.</message>
   <message level="Info" culprit="altclkctrl_0"><![CDATA["<b>clkMux</b>" instantiated <b>altclkctrl</b> "<b>altclkctrl_0</b>"]]></message>
  </messages>
 </entity>
 <entity
   path="submodules/"
   parameterizationKey="altclkctrl:21.1:CLOCK_TYPE=1,DEVICE_FAMILY=Cyclone IV E,ENA_REGISTER_MODE=1,GUI_USE_ENA=false,NUMBER_OF_CLOCKS=2,USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION=false"
   instancePathKey="clkMux:.:altclkctrl_0"
   kind="altclkctrl"
   version="21.1"
   name="clkMux_altclkctrl_0">
  <parameter name="NUMBER_OF_CLOCKS" value="2" />
  <parameter name="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION" value="false" />
  <parameter name="GUI_USE_ENA" value="false" />
  <parameter name="DEVICE_FAMILY" value="Cyclone IV E" />
  <parameter name="ENA_REGISTER_MODE" value="1" />
  <parameter name="CLOCK_TYPE" value="1" />
  <generatedFiles>
   <file
       path="/home/bart/Documents/FPGA/FPGC5/Quartus/clkMux/synthesis/submodules/clkMux_altclkctrl_0.v"
       type="VERILOG"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/home/bart/intelFPGA_lite/21.1/ip/altera/megafunctions/altclkctrl/altclkctrl_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="clkMux" as="altclkctrl_0" />
  <messages>
   <message level="Debug" culprit="clkMux">queue size: 0 starting:altclkctrl "submodules/clkMux_altclkctrl_0"</message>
   <message level="Info" culprit="altclkctrl_0">Generating top-level entity clkMux_altclkctrl_0.</message>
   <message level="Debug" culprit="altclkctrl_0">Current quartus bindir: /home/bart/intelFPGA_lite/21.1/quartus/linux64/.</message>
   <message level="Info" culprit="altclkctrl_0"><![CDATA["<b>clkMux</b>" instantiated <b>altclkctrl</b> "<b>altclkctrl_0</b>"]]></message>
  </messages>
 </entity>
</deploy>