FPGC5.qsf 13 KB

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  1. # -------------------------------------------------------------------------- #
  2. #
  3. # Copyright (C) 1991-2012 Altera Corporation
  4. # Your use of Altera Corporation's design tools, logic functions
  5. # and other software and tools, and its AMPP partner logic
  6. # functions, and any output files from any of the foregoing
  7. # (including device programming or simulation files), and any
  8. # associated documentation or information are expressly subject
  9. # to the terms and conditions of the Altera Program License
  10. # Subscription Agreement, Altera MegaCore Function License
  11. # Agreement, or other applicable license agreement, including,
  12. # without limitation, that your use is for the sole purpose of
  13. # programming logic devices manufactured by Altera and sold by
  14. # Altera or its authorized distributors. Please refer to the
  15. # applicable agreement for further details.
  16. #
  17. # -------------------------------------------------------------------------- #
  18. #
  19. # Quartus II 64-Bit
  20. # Version 12.1 Build 177 11/07/2012 SJ Full Version
  21. # Date created = 09:34:42 September 06, 2015
  22. #
  23. # -------------------------------------------------------------------------- #
  24. #
  25. # Notes:
  26. #
  27. # 1) The default values for assignments are stored in the file:
  28. # FPGC5_assignment_defaults.qdf
  29. # If this file doesn't exist, see file:
  30. # assignment_defaults.qdf
  31. #
  32. # 2) Altera recommends that you do not modify this file. This
  33. # file is updated automatically by the Quartus II software
  34. # and any changes you make may be lost or overwritten.
  35. #
  36. # -------------------------------------------------------------------------- #
  37. set_global_assignment -name FAMILY "Cyclone IV E"
  38. set_global_assignment -name DEVICE EP4CE15F23C8
  39. set_global_assignment -name TOP_LEVEL_ENTITY FPGC5
  40. set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
  41. set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:23:14 JUNE 23, 2021"
  42. set_global_assignment -name LAST_QUARTUS_VERSION "21.1.1 Lite Edition"
  43. set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
  44. set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
  45. set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
  46. set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
  47. set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
  48. set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
  49. set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
  50. set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)"
  51. set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
  52. set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
  53. set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
  54. set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
  55. set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
  56. set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
  57. set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
  58. set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
  59. set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
  60. set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
  61. set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
  62. set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
  63. set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
  64. set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
  65. set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
  66. set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
  67. set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
  68. set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
  69. set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
  70. set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
  71. set_location_assignment PIN_T2 -to clock
  72. set_location_assignment PIN_J1 -to nreset
  73. set_location_assignment PIN_E4 -to led
  74. set_location_assignment PIN_AB4 -to SDRAM_WEn
  75. set_location_assignment PIN_W7 -to SDRAM_DQM[0]
  76. set_location_assignment PIN_AB3 -to SDRAM_RASn
  77. set_location_assignment PIN_AA5 -to SDRAM_DQM[1]
  78. set_location_assignment PIN_AA3 -to SDRAM_CSn
  79. set_location_assignment PIN_Y6 -to SDRAM_CLK
  80. set_location_assignment PIN_W6 -to SDRAM_CKE
  81. set_location_assignment PIN_AA4 -to SDRAM_CASn
  82. set_location_assignment PIN_AA10 -to SDRAM_DQ[0]
  83. set_location_assignment PIN_AB9 -to SDRAM_DQ[1]
  84. set_location_assignment PIN_AA9 -to SDRAM_DQ[2]
  85. set_location_assignment PIN_AB8 -to SDRAM_DQ[3]
  86. set_location_assignment PIN_AA8 -to SDRAM_DQ[4]
  87. set_location_assignment PIN_AB7 -to SDRAM_DQ[5]
  88. set_location_assignment PIN_AA7 -to SDRAM_DQ[6]
  89. set_location_assignment PIN_AB5 -to SDRAM_DQ[7]
  90. set_location_assignment PIN_Y7 -to SDRAM_DQ[8]
  91. set_location_assignment PIN_W8 -to SDRAM_DQ[9]
  92. set_location_assignment PIN_Y8 -to SDRAM_DQ[10]
  93. set_location_assignment PIN_V9 -to SDRAM_DQ[11]
  94. set_location_assignment PIN_V10 -to SDRAM_DQ[12]
  95. set_location_assignment PIN_Y10 -to SDRAM_DQ[13]
  96. set_location_assignment PIN_W10 -to SDRAM_DQ[14]
  97. set_location_assignment PIN_V11 -to SDRAM_DQ[15]
  98. set_location_assignment PIN_Y1 -to SDRAM_BA[0]
  99. set_location_assignment PIN_W2 -to SDRAM_BA[1]
  100. set_location_assignment PIN_V2 -to SDRAM_A[0]
  101. set_location_assignment PIN_V1 -to SDRAM_A[1]
  102. set_location_assignment PIN_U2 -to SDRAM_A[2]
  103. set_location_assignment PIN_U1 -to SDRAM_A[3]
  104. set_location_assignment PIN_V3 -to SDRAM_A[4]
  105. set_location_assignment PIN_V4 -to SDRAM_A[5]
  106. set_location_assignment PIN_Y2 -to SDRAM_A[6]
  107. set_location_assignment PIN_AA1 -to SDRAM_A[7]
  108. set_location_assignment PIN_Y3 -to SDRAM_A[8]
  109. set_location_assignment PIN_V5 -to SDRAM_A[9]
  110. set_location_assignment PIN_W1 -to SDRAM_A[10]
  111. set_location_assignment PIN_Y4 -to SDRAM_A[11]
  112. set_location_assignment PIN_V6 -to SDRAM_A[12]
  113. set_location_assignment PIN_B17 -to UART0_dtr
  114. set_location_assignment PIN_B15 -to UART0_out
  115. set_location_assignment PIN_B16 -to UART0_in
  116. set_location_assignment PIN_C3 -to UART2_out
  117. set_location_assignment PIN_A5 -to UART2_in
  118. set_location_assignment PIN_B10 -to SPI0_clk
  119. set_location_assignment PIN_A15 -to SPI0_cs
  120. set_location_assignment PIN_B9 -to SPI0_data
  121. set_location_assignment PIN_B13 -to SPI0_q
  122. set_location_assignment PIN_B14 -to SPI0_wp
  123. set_location_assignment PIN_B8 -to SPI0_hold
  124. set_location_assignment PIN_R2 -to SPI1_clk
  125. set_location_assignment PIN_R1 -to SPI1_cs
  126. set_location_assignment PIN_N1 -to SPI1_mosi
  127. set_location_assignment PIN_N2 -to SPI1_miso
  128. set_location_assignment PIN_P1 -to SPI1_rst
  129. set_location_assignment PIN_P2 -to SPI1_nint
  130. set_location_assignment PIN_D2 -to SPI2_clk
  131. set_location_assignment PIN_M1 -to SPI2_cs
  132. set_location_assignment PIN_F2 -to SPI2_mosi
  133. set_location_assignment PIN_E1 -to SPI2_miso
  134. set_location_assignment PIN_H1 -to SPI2_rst
  135. set_location_assignment PIN_F1 -to SPI2_nint
  136. set_location_assignment PIN_A3 -to PS2_data
  137. set_location_assignment PIN_B2 -to PS2_clk
  138. set_location_assignment PIN_A19 -to SPI3_cs
  139. set_location_assignment PIN_B20 -to SPI3_clk
  140. set_location_assignment PIN_A20 -to SPI3_mosi
  141. set_location_assignment PIN_B18 -to SPI3_miso
  142. set_location_assignment PIN_A18 -to SPI3_nrst
  143. set_location_assignment PIN_B19 -to SPI3_int
  144. set_location_assignment PIN_AA14 -to SPI4_cs
  145. set_location_assignment PIN_AA15 -to SPI4_clk
  146. set_location_assignment PIN_AA16 -to SPI4_mosi
  147. set_location_assignment PIN_AA17 -to SPI4_miso
  148. set_location_assignment PIN_AA13 -to SPI4_gp
  149. set_location_assignment PIN_R22 -to GPI[0]
  150. set_location_assignment PIN_U22 -to GPI[1]
  151. set_location_assignment PIN_V22 -to GPI[2]
  152. set_location_assignment PIN_W22 -to GPI[3]
  153. set_location_assignment PIN_Y22 -to GPO[0]
  154. set_location_assignment PIN_AA20 -to GPO[1]
  155. set_location_assignment PIN_AA19 -to GPO[2]
  156. set_location_assignment PIN_AA18 -to GPO[3]
  157. set_location_assignment PIN_C2 -to DIPS[0]
  158. set_location_assignment PIN_H2 -to DIPS[1]
  159. set_location_assignment PIN_J2 -to DIPS[2]
  160. set_location_assignment PIN_M2 -to DIPS[3]
  161. set_location_assignment PIN_B22 -to TMDS_p[3]
  162. set_location_assignment PIN_B21 -to TMDS_n[3]
  163. set_location_assignment PIN_E22 -to TMDS_p[2]
  164. set_location_assignment PIN_E21 -to TMDS_n[2]
  165. set_location_assignment PIN_D22 -to TMDS_p[1]
  166. set_location_assignment PIN_D21 -to TMDS_n[1]
  167. set_location_assignment PIN_C22 -to TMDS_p[0]
  168. set_location_assignment PIN_C21 -to TMDS_n[0]
  169. set_location_assignment PIN_C1 -to led_Booted
  170. set_location_assignment PIN_AB17 -to led_Eth
  171. set_location_assignment PIN_AB19 -to led_Flash
  172. set_location_assignment PIN_B1 -to led_USB0
  173. set_location_assignment PIN_AB20 -to led_USB1
  174. set_location_assignment PIN_AB13 -to led_PS2
  175. set_location_assignment PIN_AB16 -to led_HDMI
  176. set_location_assignment PIN_AB18 -to led_QSPI
  177. set_location_assignment PIN_AB15 -to led_GPU
  178. set_location_assignment PIN_AB14 -to led_I2S
  179. set_location_assignment PIN_B6 -to I2S_SDIN
  180. set_location_assignment PIN_B5 -to I2S_SCLK
  181. set_location_assignment PIN_C4 -to I2S_LRCLK
  182. set_location_assignment PIN_B4 -to I2S_MCLK
  183. set_location_assignment PIN_Y21 -to composite[0]
  184. set_location_assignment PIN_W21 -to composite[1]
  185. set_location_assignment PIN_V21 -to composite[2]
  186. set_location_assignment PIN_U21 -to composite[3]
  187. set_location_assignment PIN_R21 -to composite[4]
  188. set_location_assignment PIN_P21 -to composite[5]
  189. set_location_assignment PIN_N21 -to composite[6]
  190. set_location_assignment PIN_M21 -to composite[7]
  191. set_instance_assignment -name IO_STANDARD LVDS -to TMDS_p[3]
  192. set_instance_assignment -name IO_STANDARD LVDS -to TMDS_n[3]
  193. set_instance_assignment -name IO_STANDARD LVDS -to TMDS_p[2]
  194. set_instance_assignment -name IO_STANDARD LVDS -to TMDS_n[2]
  195. set_instance_assignment -name IO_STANDARD LVDS -to TMDS_p[1]
  196. set_instance_assignment -name IO_STANDARD LVDS -to TMDS_n[1]
  197. set_instance_assignment -name IO_STANDARD LVDS -to TMDS_p[0]
  198. set_instance_assignment -name IO_STANDARD LVDS -to TMDS_n[0]
  199. set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to GPI[0]
  200. set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to GPI[1]
  201. set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to GPI[2]
  202. set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to GPI[3]
  203. set_global_assignment -name IOBANK_VCCIO 2.5V -section_id 6
  204. set_global_assignment -name OPTIMIZATION_MODE BALANCED
  205. set_location_assignment PIN_Y13 -to nBtnl
  206. set_location_assignment PIN_W13 -to nBtnr
  207. set_global_assignment -name VERILOG_FILE modules/FPGC5.v
  208. set_global_assignment -name VERILOG_FILE modules/GPU/NTSC/RGBtoYPhaseAmpl.v
  209. set_global_assignment -name VERILOG_FILE modules/GPU/NTSC/RGB332toNTSC.v
  210. set_global_assignment -name VERILOG_FILE modules/GPU/NTSC/PhaseGen.v
  211. set_global_assignment -name VERILOG_FILE modules/GPU/NTSC/NTSC.v
  212. set_global_assignment -name QIP_FILE clkMux/synthesis/clkMux.qip
  213. set_global_assignment -name VERILOG_FILE modules/GPU/FSX.v
  214. set_global_assignment -name VERILOG_FILE modules/GPU/HDMI/TMDSenc.v
  215. set_global_assignment -name VERILOG_FILE modules/GPU/HDMI/RGB2HDMI.v
  216. set_global_assignment -name VERILOG_FILE modules/GPU/TimingGenerator.v
  217. set_global_assignment -name VERILOG_FILE modules/GPU/BGWrenderer.v
  218. set_global_assignment -name VERILOG_FILE modules/IO/LEDvisualizer.v
  219. set_global_assignment -name VERILOG_FILE modules/IO/SimpleSPI.v
  220. set_global_assignment -name VERILOG_FILE modules/IO/UARTrx.v
  221. set_global_assignment -name VERILOG_FILE modules/IO/UARTtx.v
  222. set_global_assignment -name VERILOG_FILE modules/IO/OStimer.v
  223. set_global_assignment -name VERILOG_FILE modules/IO/NESpadReader.v
  224. set_global_assignment -name VERILOG_FILE modules/IO/Keyboard.v
  225. set_global_assignment -name VERILOG_FILE modules/CPU/ALU.v
  226. set_global_assignment -name VERILOG_FILE modules/CPU/Arbiter.v
  227. set_global_assignment -name VERILOG_FILE modules/CPU/ControlUnit.v
  228. set_global_assignment -name VERILOG_FILE modules/CPU/CPU.v
  229. set_global_assignment -name VERILOG_FILE modules/CPU/DataMem.v
  230. set_global_assignment -name VERILOG_FILE modules/CPU/InstrMem.v
  231. set_global_assignment -name VERILOG_FILE modules/CPU/InstructionDecoder.v
  232. set_global_assignment -name VERILOG_FILE modules/CPU/Regbank.v
  233. set_global_assignment -name VERILOG_FILE modules/CPU/Regr.v
  234. set_global_assignment -name VERILOG_FILE modules/CPU/Stack.v
  235. set_global_assignment -name VERILOG_FILE modules/CPU/IntController.v
  236. set_global_assignment -name VERILOG_FILE modules/Memory/VRAM.v
  237. set_global_assignment -name VERILOG_FILE modules/Memory/SPIreader.v
  238. set_global_assignment -name VERILOG_FILE modules/Memory/SDRAMcontroller.v
  239. set_global_assignment -name VERILOG_FILE modules/Memory/ROM.v
  240. set_global_assignment -name VERILOG_FILE modules/Memory/MemoryUnit.v
  241. set_global_assignment -name VERILOG_FILE modules/MultiStabilizer.v
  242. set_global_assignment -name VERILOG_FILE modules/DtrReset.v
  243. set_global_assignment -name QIP_FILE clock_pll.qip
  244. set_global_assignment -name QIP_FILE lvds.qip
  245. set_global_assignment -name QIP_FILE ddr.qip
  246. set_global_assignment -name SDC_FILE FPGC5.sdc
  247. set_global_assignment -name QIP_FILE NTSC_pll.qip
  248. set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top