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Bootloaders
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7e81e7fa17
Added files missing from last commit (L1I cache).
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1 year ago |
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SimTests
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28bcde6466
New SDRAM controller that uses both SDRAM chips. Now separate bus from MU for better performance, as controller runs at 100MHz. Also updated some debug code as debugging was needed. Tested working in hardware. 2x performance boost in some cases.
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1 year ago |
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Assembler.py
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ddd3d60235
Added Fixed-Point BCC library, including a FPCALC application to test it. MULTFP instruction is added to assembler, and some library functions were added during development.
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1 year ago |
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CompileInstruction.py
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01a00e1603
Update new repo link, add requirements.txt.
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8 months ago |
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buildToVerilog.sh
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28bcde6466
New SDRAM controller that uses both SDRAM chips. Now separate bus from MU for better performance, as controller runs at 100MHz. Also updated some debug code as debugging was needed. Tested working in hardware. 2x performance boost in some cases.
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1 year ago |
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compileAndSend.sh
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1026f4776c
Cleaned up some files
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2 years ago |
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simulate.sh
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1026f4776c
Cleaned up some files
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2 years ago |
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simulateCPU.sh
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9b3e3a5eb7
Initial progress with faster design.
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2 months ago |
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testbus.sh
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9b3e3a5eb7
Initial progress with faster design.
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2 months ago |
bartpleiter
9b3e3a5eb7
Initial progress with faster design.