This website works better with JavaScript
Accueil
Explorer
Aide
Connexion
bart
/
FPGC6
miroir de
https://github.com/bartpleiter/FPGC6
Suivre
1
Voter
0
Fork
0
Fichiers
Tickets
0
Wiki
Aborescence:
9ac6dafd0f
Branches
Tags
EP4CE15
cpu100mhz
fast-cpu-pipeline
main
FPGC6
/
Quartus
/
modules
/
GPU
/
HDMI
bart
e1bb01a621
Cleaned and renamed Quartus project.
il y a 1 an
..
RGB2HDMI.v
442d51ba85
Added images to documentation, HDMI is working without lvds, init of new sdram controller done.
il y a 2 ans
TMDSenc.v
b74702c915
Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram
il y a 2 ans