| .. |
|
CPU
|
9438941e15
Initial setup to simulate 100mhz cpu in verilog testbench.
|
6 tháng trước cách đây |
|
GPU
|
0fd222280a
Added halfres rendering mode to gpu and mu. Added millis counter to mu. Raycaster now renders at half resolution and many improvements. Now at 40 to 70fps.
|
1 năm trước cách đây |
|
IO
|
0fd222280a
Added halfres rendering mode to gpu and mu. Added millis counter to mu. Raycaster now renders at half resolution and many improvements. Now at 40 to 70fps.
|
1 năm trước cách đây |
|
Memory
|
9438941e15
Initial setup to simulate 100mhz cpu in verilog testbench.
|
6 tháng trước cách đây |
|
DtrReset.v
|
b74702c915
Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram
|
2 năm trước cách đây |
|
FPGC6.v
|
9438941e15
Initial setup to simulate 100mhz cpu in verilog testbench.
|
6 tháng trước cách đây |
|
MultiStabilizer.v
|
b74702c915
Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram
|
2 năm trước cách đây |
bartpleiter
9438941e15
Initial setup to simulate 100mhz cpu in verilog testbench.