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bin2txt.sh
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9662964536
Added back scripts for converting to spi.txt. Tested code to run from SPI flash, fixed cycle delay for SPI flash in output latch in MU which caused the bus_q to arrive a cycle later than bus_done.
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2 年之前 |
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code.bin
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f78729ea77
Fixed L2 cache state machine issue which was only present in the previous commit.
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1 年之前 |
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rom.list
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7e81e7fa17
Added files missing from last commit (L1I cache).
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1 年之前 |
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spi.txt
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f78729ea77
Fixed L2 cache state machine issue which was only present in the previous commit.
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1 年之前 |
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sram.list
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9438941e15
Initial setup to simulate 100mhz cpu in verilog testbench.
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6 月之前 |
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vram32.list
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916054063a
Added MU from FPGC5, created arbiter to regulate access to the CPU memory bus from both Instruction and Data memory, created fast testbench for arbiter, can now start adding arbiter and MU to CPU design
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2 年之前 |
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vram8.list
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b74702c915
Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram
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2 年之前 |
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vramPX.list
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7b14d2d273
Improved Pixel Engine.
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2 年之前 |
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vramSPR.list
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b74702c915
Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram
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2 年之前 |
bartpleiter
9438941e15
Initial setup to simulate 100mhz cpu in verilog testbench.