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bart
/
FPGC6
réplica de https://github.com/bartpleiter/FPGC6
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Árbore: 9438941e15
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bartpleiter 9438941e15 Initial setup to simulate 100mhz cpu in verilog testbench. hai 6 meses
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CPU_arch.jpg 9438941e15 Initial setup to simulate 100mhz cpu in verilog testbench. hai 6 meses
PCB_back.png 442d51ba85 Added images to documentation, HDMI is working without lvds, init of new sdram controller done. %!s(int64=2) %!d(string=hai) anos
PCB_front.png 442d51ba85 Added images to documentation, HDMI is working without lvds, init of new sdram controller done. %!s(int64=2) %!d(string=hai) anos
complete_no_ext.jpg 442d51ba85 Added images to documentation, HDMI is working without lvds, init of new sdram controller done. %!s(int64=2) %!d(string=hai) anos
gtkwave.png c1486c43e0 Documentation update. Remove subl3 files. hai 6 meses
logo_big_alpha.png 3d9b4194f7 Added initial documentation %!s(int64=2) %!d(string=hai) anos
render.jpg 442d51ba85 Added images to documentation, HDMI is working without lvds, init of new sdram controller done. %!s(int64=2) %!d(string=hai) anos
schematic.png 442d51ba85 Added images to documentation, HDMI is working without lvds, init of new sdram controller done. %!s(int64=2) %!d(string=hai) anos
soldered.jpg 442d51ba85 Added images to documentation, HDMI is working without lvds, init of new sdram controller done. %!s(int64=2) %!d(string=hai) anos
vvp.png c1486c43e0 Documentation update. Remove subl3 files. hai 6 meses