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Bootloaders
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7e81e7fa17
Added files missing from last commit (L1I cache).
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1 year ago |
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SimTests
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28bcde6466
New SDRAM controller that uses both SDRAM chips. Now separate bus from MU for better performance, as controller runs at 100MHz. Also updated some debug code as debugging was needed. Tested working in hardware. 2x performance boost in some cases.
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1 year ago |
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Assembler.py
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7e81e7fa17
Added files missing from last commit (L1I cache).
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1 year ago |
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CompileInstruction.py
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7e81e7fa17
Added files missing from last commit (L1I cache).
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1 year ago |
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buildToVerilog.sh
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28bcde6466
New SDRAM controller that uses both SDRAM chips. Now separate bus from MU for better performance, as controller runs at 100MHz. Also updated some debug code as debugging was needed. Tested working in hardware. 2x performance boost in some cases.
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1 year ago |
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compileAndSend.sh
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1026f4776c
Cleaned up some files
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2 years ago |
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simulate.sh
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1026f4776c
Cleaned up some files
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2 years ago |
bart
7e81e7fa17
Added files missing from last commit (L1I cache).