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Arbiter.v 1.9 KB

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  1. /*
  2. * Arbiter
  3. * Regulates access to the CPU memory bus from both Instruction and Data memory
  4. * In case of two requests at the same time, Data memory is granted first
  5. */
  6. module Arbiter(
  7. input clk,
  8. input reset,
  9. // port a (Instr)
  10. input [31:0] addr_a,
  11. input [31:0] data_a,
  12. input we_a,
  13. input start_a,
  14. output done_a,
  15. // port b (Data)
  16. input [31:0] addr_b,
  17. input [31:0] data_b,
  18. input we_b,
  19. input start_b,
  20. output done_b,
  21. // output (both ports)
  22. output [31:0] q,
  23. // bus
  24. output reg [26:0] bus_addr = 27'd0,
  25. output reg [31:0] bus_data = 32'd0,
  26. output reg bus_we = 1'b0,
  27. output bus_start,
  28. input [31:0] bus_q,
  29. input bus_done
  30. );
  31. assign q = bus_q;
  32. assign done_a = busy_a && !busy_b && bus_done;
  33. assign done_b = busy_b && bus_done;
  34. reg busy_a = 1'b0;
  35. reg busy_b = 1'b0;
  36. reg bus_start_reg = 1'b0;
  37. assign bus_start = (bus_start_reg) && (!bus_done);
  38. always @(posedge clk)
  39. begin
  40. if (reset)
  41. begin
  42. bus_start_reg <= 1'b0;
  43. bus_addr <= 27'd0;
  44. bus_data <= 32'd0;
  45. bus_we <= 1'b0;
  46. busy_b <= 1'b0;
  47. busy_a <= 1'b0;
  48. end
  49. else
  50. begin
  51. if (start_b && (!busy_a || bus_done))
  52. begin
  53. bus_start_reg <= 1'b1;
  54. bus_addr <= addr_b;
  55. bus_data <= data_b;
  56. bus_we <= we_b;
  57. busy_b <= 1'b1;
  58. end
  59. else if (start_a && (!busy_b || bus_done))
  60. begin
  61. bus_start_reg <= 1'b1;
  62. bus_addr <= addr_a;
  63. bus_data <= data_a;
  64. bus_we <= we_a;
  65. busy_a <= 1'b1;
  66. end
  67. if (bus_done)
  68. begin
  69. if (!busy_b)
  70. begin
  71. busy_a <= 1'b0;
  72. end
  73. busy_b <= 1'b0;
  74. bus_start_reg <= 1'b0;
  75. end
  76. end
  77. end
  78. endmodule