ddr.v 4.1 KB

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  1. // megafunction wizard: %ALTDDIO_OUT%
  2. // GENERATION: STANDARD
  3. // VERSION: WM1.0
  4. // MODULE: ALTDDIO_OUT
  5. // ============================================================
  6. // File Name: ddr.v
  7. // Megafunction Name(s):
  8. // ALTDDIO_OUT
  9. //
  10. // Simulation Library Files(s):
  11. //
  12. // ============================================================
  13. // ************************************************************
  14. // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
  15. //
  16. // 21.1.1 Build 850 06/23/2022 SJ Lite Edition
  17. // ************************************************************
  18. //Copyright (C) 2022 Intel Corporation. All rights reserved.
  19. //Your use of Intel Corporation's design tools, logic functions
  20. //and other software and tools, and any partner logic
  21. //functions, and any output files from any of the foregoing
  22. //(including device programming or simulation files), and any
  23. //associated documentation or information are expressly subject
  24. //to the terms and conditions of the Intel Program License
  25. //Subscription Agreement, the Intel Quartus Prime License Agreement,
  26. //the Intel FPGA IP License Agreement, or other applicable license
  27. //agreement, including, without limitation, that your use is for
  28. //the sole purpose of programming logic devices manufactured by
  29. //Intel and sold by Intel or its authorized distributors. Please
  30. //refer to the applicable agreement for further details, at
  31. //https://fpgasoftware.intel.com/eula.
  32. // synopsys translate_off
  33. `timescale 1 ps / 1 ps
  34. // synopsys translate_on
  35. module ddr (
  36. datain_h,
  37. datain_l,
  38. outclock,
  39. dataout);
  40. input [0:0] datain_h;
  41. input [0:0] datain_l;
  42. input outclock;
  43. output [0:0] dataout;
  44. wire [0:0] sub_wire0;
  45. wire [0:0] dataout = sub_wire0[0:0];
  46. altddio_out ALTDDIO_OUT_component (
  47. .datain_h (datain_h),
  48. .datain_l (datain_l),
  49. .outclock (outclock),
  50. .dataout (sub_wire0),
  51. .aclr (1'b0),
  52. .aset (1'b0),
  53. .oe (1'b1),
  54. .oe_out (),
  55. .outclocken (1'b1),
  56. .sclr (1'b0),
  57. .sset (1'b0));
  58. defparam
  59. ALTDDIO_OUT_component.extend_oe_disable = "OFF",
  60. ALTDDIO_OUT_component.intended_device_family = "Cyclone IV E",
  61. ALTDDIO_OUT_component.invert_output = "OFF",
  62. ALTDDIO_OUT_component.lpm_hint = "UNUSED",
  63. ALTDDIO_OUT_component.lpm_type = "altddio_out",
  64. ALTDDIO_OUT_component.oe_reg = "UNREGISTERED",
  65. ALTDDIO_OUT_component.power_up_high = "OFF",
  66. ALTDDIO_OUT_component.width = 1;
  67. endmodule
  68. // ============================================================
  69. // CNX file retrieval info
  70. // ============================================================
  71. // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
  72. // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
  73. // Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF"
  74. // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
  75. // Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
  76. // Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
  77. // Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
  78. // Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED"
  79. // Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
  80. // Retrieval info: CONSTANT: WIDTH NUMERIC "1"
  81. // Retrieval info: USED_PORT: datain_h 0 0 1 0 INPUT NODEFVAL "datain_h[0..0]"
  82. // Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 1 0
  83. // Retrieval info: USED_PORT: datain_l 0 0 1 0 INPUT NODEFVAL "datain_l[0..0]"
  84. // Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 1 0
  85. // Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]"
  86. // Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0
  87. // Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock"
  88. // Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
  89. // Retrieval info: GEN_FILE: TYPE_NORMAL ddr.v TRUE FALSE
  90. // Retrieval info: GEN_FILE: TYPE_NORMAL ddr.qip TRUE FALSE
  91. // Retrieval info: GEN_FILE: TYPE_NORMAL ddr.bsf FALSE TRUE
  92. // Retrieval info: GEN_FILE: TYPE_NORMAL ddr_inst.v FALSE TRUE
  93. // Retrieval info: GEN_FILE: TYPE_NORMAL ddr_bb.v TRUE TRUE
  94. // Retrieval info: GEN_FILE: TYPE_NORMAL ddr.inc FALSE TRUE
  95. // Retrieval info: GEN_FILE: TYPE_NORMAL ddr.cmp FALSE TRUE
  96. // Retrieval info: GEN_FILE: TYPE_NORMAL ddr.ppf TRUE FALSE