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ncsim_setup.sh 8.3 KB

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  1. # (C) 2001-2022 Altera Corporation. All rights reserved.
  2. # Your use of Altera Corporation's design tools, logic functions and
  3. # other software and tools, and its AMPP partner logic functions, and
  4. # any output files any of the foregoing (including device programming
  5. # or simulation files), and any associated documentation or information
  6. # are expressly subject to the terms and conditions of the Altera
  7. # Program License Subscription Agreement, Altera MegaCore Function
  8. # License Agreement, or other applicable license agreement, including,
  9. # without limitation, that your use is for the sole purpose of
  10. # programming logic devices manufactured by Altera and sold by Altera
  11. # or its authorized distributors. Please refer to the applicable
  12. # agreement for further details.
  13. # ACDS 21.1 850 linux 2022.07.04.11:59:13
  14. # ----------------------------------------
  15. # ncsim - auto-generated simulation script
  16. # ----------------------------------------
  17. # This script provides commands to simulate the following IP detected in
  18. # your Quartus project:
  19. # clkMux
  20. #
  21. # Altera recommends that you source this Quartus-generated IP simulation
  22. # script from your own customized top-level script, and avoid editing this
  23. # generated script.
  24. #
  25. # To write a top-level shell script that compiles Altera simulation libraries
  26. # and the Quartus-generated IP in your project, along with your design and
  27. # testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
  28. # into a new file, e.g. named "ncsim.sh", and modify text as directed.
  29. #
  30. # You can also modify the simulation flow to suit your needs. Set the
  31. # following variables to 1 to disable their corresponding processes:
  32. # - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
  33. # - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
  34. # - SKIP_COM: skip compiling Quartus-generated IP simulation files
  35. # - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
  36. #
  37. # ----------------------------------------
  38. # # TOP-LEVEL TEMPLATE - BEGIN
  39. # #
  40. # # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
  41. # # construct paths to the files required to simulate the IP in your Quartus
  42. # # project. By default, the IP script assumes that you are launching the
  43. # # simulator from the IP script location. If launching from another
  44. # # location, set QSYS_SIMDIR to the output directory you specified when you
  45. # # generated the IP script, relative to the directory from which you launch
  46. # # the simulator. In this case, you must also copy the generated files
  47. # # "cds.lib" and "hdl.var" - plus the directory "cds_libs" if generated -
  48. # # into the location from which you launch the simulator, or incorporate
  49. # # into any existing library setup.
  50. # #
  51. # # Run Quartus-generated IP simulation script once to compile Quartus EDA
  52. # # simulation libraries and Quartus-generated IP simulation files, and copy
  53. # # any ROM/RAM initialization files to the simulation directory.
  54. # # - If necessary, specify any compilation options:
  55. # # USER_DEFINED_COMPILE_OPTIONS
  56. # # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
  57. # # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
  58. # #
  59. # source <script generation output directory>/cadence/ncsim_setup.sh \
  60. # SKIP_ELAB=1 \
  61. # SKIP_SIM=1 \
  62. # USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
  63. # USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
  64. # USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
  65. # QSYS_SIMDIR=<script generation output directory>
  66. # #
  67. # # Compile all design files and testbench files, including the top level.
  68. # # (These are all the files required for simulation other than the files
  69. # # compiled by the IP script)
  70. # #
  71. # ncvlog <compilation options> <design and testbench files>
  72. # #
  73. # # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
  74. # # testbench module/entity name.
  75. # #
  76. # # Run the IP script again to elaborate and simulate the top level:
  77. # # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
  78. # # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
  79. # # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
  80. # #
  81. # source <script generation output directory>/cadence/ncsim_setup.sh \
  82. # SKIP_FILE_COPY=1 \
  83. # SKIP_DEV_COM=1 \
  84. # SKIP_COM=1 \
  85. # TOP_LEVEL_NAME=<simulation top> \
  86. # USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
  87. # USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
  88. # #
  89. # # TOP-LEVEL TEMPLATE - END
  90. # ----------------------------------------
  91. #
  92. # IP SIMULATION SCRIPT
  93. # ----------------------------------------
  94. # If clkMux is one of several IP cores in your
  95. # Quartus project, you can generate a simulation script
  96. # suitable for inclusion in your top-level simulation
  97. # script by running the following command line:
  98. #
  99. # ip-setup-simulation --quartus-project=<quartus project>
  100. #
  101. # ip-setup-simulation will discover the Altera IP
  102. # within the Quartus project, and generate a unified
  103. # script which supports all the Altera IP within the design.
  104. # ----------------------------------------
  105. # ACDS 21.1 850 linux 2022.07.04.11:59:13
  106. # ----------------------------------------
  107. # initialize variables
  108. TOP_LEVEL_NAME="clkMux"
  109. QSYS_SIMDIR="./../"
  110. QUARTUS_INSTALL_DIR="/home/bart/intelFPGA_lite/21.1/quartus/"
  111. SKIP_FILE_COPY=0
  112. SKIP_DEV_COM=0
  113. SKIP_COM=0
  114. SKIP_ELAB=0
  115. SKIP_SIM=0
  116. USER_DEFINED_ELAB_OPTIONS=""
  117. USER_DEFINED_SIM_OPTIONS="-input \"@run 100; exit\""
  118. # ----------------------------------------
  119. # overwrite variables - DO NOT MODIFY!
  120. # This block evaluates each command line argument, typically used for
  121. # overwriting variables. An example usage:
  122. # sh <simulator>_setup.sh SKIP_SIM=1
  123. for expression in "$@"; do
  124. eval $expression
  125. if [ $? -ne 0 ]; then
  126. echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
  127. exit $?
  128. fi
  129. done
  130. # ----------------------------------------
  131. # initialize simulation properties - DO NOT MODIFY!
  132. ELAB_OPTIONS=""
  133. SIM_OPTIONS=""
  134. if [[ `ncsim -version` != *"ncsim(64)"* ]]; then
  135. :
  136. else
  137. :
  138. fi
  139. # ----------------------------------------
  140. # create compilation libraries
  141. mkdir -p ./libraries/work/
  142. mkdir -p ./libraries/altclkctrl_0/
  143. mkdir -p ./libraries/altera_ver/
  144. mkdir -p ./libraries/lpm_ver/
  145. mkdir -p ./libraries/sgate_ver/
  146. mkdir -p ./libraries/altera_mf_ver/
  147. mkdir -p ./libraries/altera_lnsim_ver/
  148. mkdir -p ./libraries/cycloneive_ver/
  149. # ----------------------------------------
  150. # copy RAM/ROM files to simulation directory
  151. # ----------------------------------------
  152. # compile device library files
  153. if [ $SKIP_DEV_COM -eq 0 ]; then
  154. ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
  155. ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
  156. ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
  157. ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
  158. ncvlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
  159. ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cycloneive_atoms.v" -work cycloneive_ver
  160. fi
  161. # ----------------------------------------
  162. # compile design files in correct order
  163. if [ $SKIP_COM -eq 0 ]; then
  164. ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/submodules/clkMux_altclkctrl_0.v" -work altclkctrl_0 -cdslib ./cds_libs/altclkctrl_0.cds.lib
  165. ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/clkMux.v"
  166. fi
  167. # ----------------------------------------
  168. # elaborate top level design
  169. if [ $SKIP_ELAB -eq 0 ]; then
  170. export GENERIC_PARAM_COMPAT_CHECK=1
  171. ncelab -access +w+r+c -namemap_mixgen $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
  172. fi
  173. # ----------------------------------------
  174. # simulate
  175. if [ $SKIP_SIM -eq 0 ]; then
  176. eval ncsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME
  177. fi