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rivierapro_setup.tcl 11 KB

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  1. # (C) 2001-2022 Altera Corporation. All rights reserved.
  2. # Your use of Altera Corporation's design tools, logic functions and
  3. # other software and tools, and its AMPP partner logic functions, and
  4. # any output files any of the foregoing (including device programming
  5. # or simulation files), and any associated documentation or information
  6. # are expressly subject to the terms and conditions of the Altera
  7. # Program License Subscription Agreement, Altera MegaCore Function
  8. # License Agreement, or other applicable license agreement, including,
  9. # without limitation, that your use is for the sole purpose of
  10. # programming logic devices manufactured by Altera and sold by Altera
  11. # or its authorized distributors. Please refer to the applicable
  12. # agreement for further details.
  13. # ACDS 21.1 850 linux 2022.07.04.11:59:13
  14. # ----------------------------------------
  15. # Auto-generated simulation script rivierapro_setup.tcl
  16. # ----------------------------------------
  17. # This script provides commands to simulate the following IP detected in
  18. # your Quartus project:
  19. # clkMux
  20. #
  21. # Altera recommends that you source this Quartus-generated IP simulation
  22. # script from your own customized top-level script, and avoid editing this
  23. # generated script.
  24. #
  25. # To write a top-level script that compiles Altera simulation libraries and
  26. # the Quartus-generated IP in your project, along with your design and
  27. # testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
  28. # into a new file, e.g. named "aldec.do", and modify the text as directed.
  29. #
  30. # ----------------------------------------
  31. # # TOP-LEVEL TEMPLATE - BEGIN
  32. # #
  33. # # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
  34. # # construct paths to the files required to simulate the IP in your Quartus
  35. # # project. By default, the IP script assumes that you are launching the
  36. # # simulator from the IP script location. If launching from another
  37. # # location, set QSYS_SIMDIR to the output directory you specified when you
  38. # # generated the IP script, relative to the directory from which you launch
  39. # # the simulator.
  40. # #
  41. # set QSYS_SIMDIR <script generation output directory>
  42. # #
  43. # # Source the generated IP simulation script.
  44. # source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
  45. # #
  46. # # Set any compilation options you require (this is unusual).
  47. # set USER_DEFINED_COMPILE_OPTIONS <compilation options>
  48. # set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
  49. # set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
  50. # #
  51. # # Call command to compile the Quartus EDA simulation library.
  52. # dev_com
  53. # #
  54. # # Call command to compile the Quartus-generated IP simulation files.
  55. # com
  56. # #
  57. # # Add commands to compile all design files and testbench files, including
  58. # # the top level. (These are all the files required for simulation other
  59. # # than the files compiled by the Quartus-generated IP simulation script)
  60. # #
  61. # vlog -sv2k5 <your compilation options> <design and testbench files>
  62. # #
  63. # # Set the top-level simulation or testbench module/entity name, which is
  64. # # used by the elab command to elaborate the top level.
  65. # #
  66. # set TOP_LEVEL_NAME <simulation top>
  67. # #
  68. # # Set any elaboration options you require.
  69. # set USER_DEFINED_ELAB_OPTIONS <elaboration options>
  70. # #
  71. # # Call command to elaborate your design and testbench.
  72. # elab
  73. # #
  74. # # Run the simulation.
  75. # run
  76. # #
  77. # # Report success to the shell.
  78. # exit -code 0
  79. # #
  80. # # TOP-LEVEL TEMPLATE - END
  81. # ----------------------------------------
  82. #
  83. # IP SIMULATION SCRIPT
  84. # ----------------------------------------
  85. # If clkMux is one of several IP cores in your
  86. # Quartus project, you can generate a simulation script
  87. # suitable for inclusion in your top-level simulation
  88. # script by running the following command line:
  89. #
  90. # ip-setup-simulation --quartus-project=<quartus project>
  91. #
  92. # ip-setup-simulation will discover the Altera IP
  93. # within the Quartus project, and generate a unified
  94. # script which supports all the Altera IP within the design.
  95. # ----------------------------------------
  96. # ----------------------------------------
  97. # Initialize variables
  98. if ![info exists SYSTEM_INSTANCE_NAME] {
  99. set SYSTEM_INSTANCE_NAME ""
  100. } elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
  101. set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
  102. }
  103. if ![info exists TOP_LEVEL_NAME] {
  104. set TOP_LEVEL_NAME "clkMux"
  105. }
  106. if ![info exists QSYS_SIMDIR] {
  107. set QSYS_SIMDIR "./../"
  108. }
  109. if ![info exists QUARTUS_INSTALL_DIR] {
  110. set QUARTUS_INSTALL_DIR "/home/bart/intelFPGA_lite/21.1/quartus/"
  111. }
  112. if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
  113. set USER_DEFINED_COMPILE_OPTIONS ""
  114. }
  115. if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] {
  116. set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
  117. }
  118. if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] {
  119. set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
  120. }
  121. if ![info exists USER_DEFINED_ELAB_OPTIONS] {
  122. set USER_DEFINED_ELAB_OPTIONS ""
  123. }
  124. # ----------------------------------------
  125. # Initialize simulation properties - DO NOT MODIFY!
  126. set ELAB_OPTIONS ""
  127. set SIM_OPTIONS ""
  128. if ![ string match "*-64 vsim*" [ vsim -version ] ] {
  129. } else {
  130. }
  131. set Aldec "Riviera"
  132. if { [ string match "*Active-HDL*" [ vsim -version ] ] } {
  133. set Aldec "Active"
  134. }
  135. if { [ string match "Active" $Aldec ] } {
  136. scripterconf -tcl
  137. createdesign "$TOP_LEVEL_NAME" "."
  138. opendesign "$TOP_LEVEL_NAME"
  139. }
  140. # ----------------------------------------
  141. # Copy ROM/RAM files to simulation directory
  142. alias file_copy {
  143. echo "\[exec\] file_copy"
  144. }
  145. # ----------------------------------------
  146. # Create compilation libraries
  147. proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
  148. ensure_lib ./libraries
  149. ensure_lib ./libraries/work
  150. vmap work ./libraries/work
  151. ensure_lib ./libraries/altera_ver
  152. vmap altera_ver ./libraries/altera_ver
  153. ensure_lib ./libraries/lpm_ver
  154. vmap lpm_ver ./libraries/lpm_ver
  155. ensure_lib ./libraries/sgate_ver
  156. vmap sgate_ver ./libraries/sgate_ver
  157. ensure_lib ./libraries/altera_mf_ver
  158. vmap altera_mf_ver ./libraries/altera_mf_ver
  159. ensure_lib ./libraries/altera_lnsim_ver
  160. vmap altera_lnsim_ver ./libraries/altera_lnsim_ver
  161. ensure_lib ./libraries/cycloneive_ver
  162. vmap cycloneive_ver ./libraries/cycloneive_ver
  163. ensure_lib ./libraries/altclkctrl_0
  164. vmap altclkctrl_0 ./libraries/altclkctrl_0
  165. # ----------------------------------------
  166. # Compile device library files
  167. alias dev_com {
  168. echo "\[exec\] dev_com"
  169. eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
  170. vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
  171. vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
  172. vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
  173. vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
  174. vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cycloneive_atoms.v" -work cycloneive_ver
  175. }
  176. # ----------------------------------------
  177. # Compile the design files in correct order
  178. alias com {
  179. echo "\[exec\] com"
  180. eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/submodules/clkMux_altclkctrl_0.v" -work altclkctrl_0
  181. eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/clkMux.v"
  182. }
  183. # ----------------------------------------
  184. # Elaborate top level design
  185. alias elab {
  186. echo "\[exec\] elab"
  187. eval vsim +access +r -t ps $ELAB_OPTIONS -L work -L altclkctrl_0 -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver $TOP_LEVEL_NAME
  188. }
  189. # ----------------------------------------
  190. # Elaborate the top level design with -dbg -O2 option
  191. alias elab_debug {
  192. echo "\[exec\] elab_debug"
  193. eval vsim -dbg -O2 +access +r -t ps $ELAB_OPTIONS -L work -L altclkctrl_0 -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver $TOP_LEVEL_NAME
  194. }
  195. # ----------------------------------------
  196. # Compile all the design files and elaborate the top level design
  197. alias ld "
  198. dev_com
  199. com
  200. elab
  201. "
  202. # ----------------------------------------
  203. # Compile all the design files and elaborate the top level design with -dbg -O2
  204. alias ld_debug "
  205. dev_com
  206. com
  207. elab_debug
  208. "
  209. # ----------------------------------------
  210. # Print out user commmand line aliases
  211. alias h {
  212. echo "List Of Command Line Aliases"
  213. echo
  214. echo "file_copy -- Copy ROM/RAM files to simulation directory"
  215. echo
  216. echo "dev_com -- Compile device library files"
  217. echo
  218. echo "com -- Compile the design files in correct order"
  219. echo
  220. echo "elab -- Elaborate top level design"
  221. echo
  222. echo "elab_debug -- Elaborate the top level design with -dbg -O2 option"
  223. echo
  224. echo "ld -- Compile all the design files and elaborate the top level design"
  225. echo
  226. echo "ld_debug -- Compile all the design files and elaborate the top level design with -dbg -O2"
  227. echo
  228. echo
  229. echo
  230. echo "List Of Variables"
  231. echo
  232. echo "TOP_LEVEL_NAME -- Top level module name."
  233. echo " For most designs, this should be overridden"
  234. echo " to enable the elab/elab_debug aliases."
  235. echo
  236. echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
  237. echo
  238. echo "QSYS_SIMDIR -- Platform Designer base simulation directory."
  239. echo
  240. echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
  241. echo
  242. echo "USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases."
  243. echo
  244. echo "USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases."
  245. echo
  246. echo "USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases."
  247. echo
  248. echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases."
  249. }
  250. file_copy
  251. h