clkMux_generation_previous.rpt 2.0 KB

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  1. Info: Starting: Create block symbol file (.bsf)
  2. Info: qsys-generate /home/bart/Documents/FPGA/FPGC5/Quartus/clkMux.qsys --block-symbol-file --output-directory=/home/bart/Documents/FPGA/FPGC5/Quartus/clkMux --family="Cyclone IV E" --part=EP4CE15F23C8
  3. Progress: Loading Quartus/clkMux.qsys
  4. Progress: Reading input file
  5. Progress: Adding altclkctrl_0 [altclkctrl 20.1]
  6. Progress: Parameterizing module altclkctrl_0
  7. Progress: Building connections
  8. Progress: Parameterizing connections
  9. Progress: Validating
  10. Progress: Done reading input file
  11. : clkMux.altclkctrl_0: Targeting device family: Cyclone IV E.
  12. : clkMux.altclkctrl_0: Global clock network allows a clock signal to reach all parts of the chip with the same amount of skew. Input port 'clkselect' can be used to switch between four clock inputs.
  13. Info: qsys-generate succeeded.
  14. Info: Finished: Create block symbol file (.bsf)
  15. Info:
  16. Info: Starting: Create HDL design files for synthesis
  17. Info: qsys-generate /home/bart/Documents/FPGA/FPGC5/Quartus/clkMux.qsys --synthesis=VERILOG --output-directory=/home/bart/Documents/FPGA/FPGC5/Quartus/clkMux/synthesis --family="Cyclone IV E" --part=EP4CE15F23C8
  18. Progress: Loading Quartus/clkMux.qsys
  19. Progress: Reading input file
  20. Progress: Adding altclkctrl_0 [altclkctrl 20.1]
  21. Progress: Parameterizing module altclkctrl_0
  22. Progress: Building connections
  23. Progress: Parameterizing connections
  24. Progress: Validating
  25. Progress: Done reading input file
  26. : clkMux.altclkctrl_0: Targeting device family: Cyclone IV E.
  27. : clkMux.altclkctrl_0: Global clock network allows a clock signal to reach all parts of the chip with the same amount of skew. Input port 'clkselect' can be used to switch between four clock inputs.
  28. Info: clkMux: Generating clkMux "clkMux" for QUARTUS_SYNTH
  29. Info: altclkctrl_0: Generating top-level entity clkMux_altclkctrl_0.
  30. Info: altclkctrl_0: "clkMux" instantiated altclkctrl "altclkctrl_0"
  31. Info: clkMux: Done "clkMux" with 2 modules, 2 files
  32. Info: qsys-generate succeeded.
  33. Info: Finished: Create HDL design files for synthesis