clkMux.xml 5.9 KB

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  1. <?xml version="1.0" encoding="UTF-8"?>
  2. <deploy
  3. date="2022.07.04.11:59:14"
  4. outputDirectory="/home/bart/Documents/FPGA/FPGC5/Quartus/clkMux/">
  5. <perimeter>
  6. <parameter
  7. name="AUTO_GENERATION_ID"
  8. type="Integer"
  9. defaultValue="0"
  10. onHdl="0"
  11. affectsHdl="1" />
  12. <parameter
  13. name="AUTO_UNIQUE_ID"
  14. type="String"
  15. defaultValue=""
  16. onHdl="0"
  17. affectsHdl="1" />
  18. <parameter
  19. name="AUTO_DEVICE_FAMILY"
  20. type="String"
  21. defaultValue="Cyclone IV E"
  22. onHdl="0"
  23. affectsHdl="1" />
  24. <parameter
  25. name="AUTO_DEVICE"
  26. type="String"
  27. defaultValue="EP4CE15F23C8"
  28. onHdl="0"
  29. affectsHdl="1" />
  30. <parameter
  31. name="AUTO_DEVICE_SPEEDGRADE"
  32. type="String"
  33. defaultValue="8"
  34. onHdl="0"
  35. affectsHdl="1" />
  36. <interface name="altclkctrl_input" kind="conduit" start="0">
  37. <property name="associatedClock" value="" />
  38. <property name="associatedReset" value="" />
  39. <port name="inclk1x" direction="input" role="inclk1x" width="1" />
  40. <port name="inclk0x" direction="input" role="inclk0x" width="1" />
  41. <port name="clkselect" direction="input" role="clkselect" width="1" />
  42. </interface>
  43. <interface name="altclkctrl_output" kind="conduit" start="0">
  44. <property name="associatedClock" value="" />
  45. <property name="associatedReset" value="" />
  46. <port name="outclk" direction="output" role="outclk" width="1" />
  47. </interface>
  48. </perimeter>
  49. <entity
  50. path=""
  51. parameterizationKey="clkMux:1.0:AUTO_DEVICE=EP4CE15F23C8,AUTO_DEVICE_FAMILY=Cyclone IV E,AUTO_DEVICE_SPEEDGRADE=8,AUTO_GENERATION_ID=1656928754,AUTO_UNIQUE_ID=(altclkctrl:21.1:CLOCK_TYPE=1,DEVICE_FAMILY=Cyclone IV E,ENA_REGISTER_MODE=1,GUI_USE_ENA=false,NUMBER_OF_CLOCKS=2,USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION=false)"
  52. instancePathKey="clkMux"
  53. kind="clkMux"
  54. version="1.0"
  55. name="clkMux">
  56. <parameter name="AUTO_GENERATION_ID" value="1656928754" />
  57. <parameter name="AUTO_DEVICE" value="EP4CE15F23C8" />
  58. <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
  59. <parameter name="AUTO_UNIQUE_ID" value="" />
  60. <parameter name="AUTO_DEVICE_SPEEDGRADE" value="8" />
  61. <generatedFiles>
  62. <file
  63. path="/home/bart/Documents/FPGA/FPGC5/Quartus/clkMux/synthesis/clkMux.v"
  64. type="VERILOG" />
  65. </generatedFiles>
  66. <childGeneratedFiles>
  67. <file
  68. path="/home/bart/Documents/FPGA/FPGC5/Quartus/clkMux/synthesis/submodules/clkMux_altclkctrl_0.v"
  69. type="VERILOG"
  70. attributes="" />
  71. </childGeneratedFiles>
  72. <sourceFiles>
  73. <file path="/home/bart/Documents/FPGA/FPGC5/Quartus/clkMux.qsys" />
  74. </sourceFiles>
  75. <childSourceFiles>
  76. <file
  77. path="/home/bart/intelFPGA_lite/21.1/ip/altera/megafunctions/altclkctrl/altclkctrl_hw.tcl" />
  78. </childSourceFiles>
  79. <messages>
  80. <message level="Debug" culprit="clkMux">queue size: 0 starting:clkMux "clkMux"</message>
  81. <message level="Progress" culprit="min"></message>
  82. <message level="Progress" culprit="max"></message>
  83. <message level="Progress" culprit="current"></message>
  84. <message level="Debug">Transform: CustomInstructionTransform</message>
  85. <message level="Debug">No custom instruction connections, skipping transform </message>
  86. <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>1</b> modules, <b>0</b> connections]]></message>
  87. <message level="Debug">Transform: MMTransform</message>
  88. <message level="Debug">Transform: InterruptMapperTransform</message>
  89. <message level="Debug">Transform: InterruptSyncTransform</message>
  90. <message level="Debug">Transform: InterruptFanoutTransform</message>
  91. <message level="Debug">Transform: AvalonStreamingTransform</message>
  92. <message level="Debug">Transform: ResetAdaptation</message>
  93. <message level="Debug" culprit="clkMux"><![CDATA["<b>clkMux</b>" reuses <b>altclkctrl</b> "<b>submodules/clkMux_altclkctrl_0</b>"]]></message>
  94. <message level="Debug" culprit="clkMux">queue size: 0 starting:altclkctrl "submodules/clkMux_altclkctrl_0"</message>
  95. <message level="Info" culprit="altclkctrl_0">Generating top-level entity clkMux_altclkctrl_0.</message>
  96. <message level="Debug" culprit="altclkctrl_0">Current quartus bindir: /home/bart/intelFPGA_lite/21.1/quartus/linux64/.</message>
  97. <message level="Info" culprit="altclkctrl_0"><![CDATA["<b>clkMux</b>" instantiated <b>altclkctrl</b> "<b>altclkctrl_0</b>"]]></message>
  98. </messages>
  99. </entity>
  100. <entity
  101. path="submodules/"
  102. parameterizationKey="altclkctrl:21.1:CLOCK_TYPE=1,DEVICE_FAMILY=Cyclone IV E,ENA_REGISTER_MODE=1,GUI_USE_ENA=false,NUMBER_OF_CLOCKS=2,USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION=false"
  103. instancePathKey="clkMux:.:altclkctrl_0"
  104. kind="altclkctrl"
  105. version="21.1"
  106. name="clkMux_altclkctrl_0">
  107. <parameter name="NUMBER_OF_CLOCKS" value="2" />
  108. <parameter name="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION" value="false" />
  109. <parameter name="GUI_USE_ENA" value="false" />
  110. <parameter name="DEVICE_FAMILY" value="Cyclone IV E" />
  111. <parameter name="ENA_REGISTER_MODE" value="1" />
  112. <parameter name="CLOCK_TYPE" value="1" />
  113. <generatedFiles>
  114. <file
  115. path="/home/bart/Documents/FPGA/FPGC5/Quartus/clkMux/synthesis/submodules/clkMux_altclkctrl_0.v"
  116. type="VERILOG"
  117. attributes="" />
  118. </generatedFiles>
  119. <childGeneratedFiles/>
  120. <sourceFiles>
  121. <file
  122. path="/home/bart/intelFPGA_lite/21.1/ip/altera/megafunctions/altclkctrl/altclkctrl_hw.tcl" />
  123. </sourceFiles>
  124. <childSourceFiles/>
  125. <instantiator instantiator="clkMux" as="altclkctrl_0" />
  126. <messages>
  127. <message level="Debug" culprit="clkMux">queue size: 0 starting:altclkctrl "submodules/clkMux_altclkctrl_0"</message>
  128. <message level="Info" culprit="altclkctrl_0">Generating top-level entity clkMux_altclkctrl_0.</message>
  129. <message level="Debug" culprit="altclkctrl_0">Current quartus bindir: /home/bart/intelFPGA_lite/21.1/quartus/linux64/.</message>
  130. <message level="Info" culprit="altclkctrl_0"><![CDATA["<b>clkMux</b>" instantiated <b>altclkctrl</b> "<b>altclkctrl_0</b>"]]></message>
  131. </messages>
  132. </entity>
  133. </deploy>