FPGC6/Quartus/FPGC5.qsf

# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2012 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors.  Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 12.1 Build 177 11/07/2012 SJ Full Version
# Date created = 09:34:42  September 06, 2015
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		FPGC5_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE15F23C8
set_global_assignment -name TOP_LEVEL_ENTITY FPGC5
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:23:14  JUNE 23, 2021"
set_global_assignment -name LAST_QUARTUS_VERSION "21.1.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_T2 -to clock
set_location_assignment PIN_J1 -to nreset
set_location_assignment PIN_E4 -to led
set_location_assignment PIN_AB4 -to SDRAM_WEn
set_location_assignment PIN_W7 -to SDRAM_DQM[0]
set_location_assignment PIN_AB3 -to SDRAM_RASn
set_location_assignment PIN_AA5 -to SDRAM_DQM[1]
set_location_assignment PIN_AA3 -to SDRAM_CSn
set_location_assignment PIN_Y6 -to SDRAM_CLK
set_location_assignment PIN_W6 -to SDRAM_CKE
set_location_assignment PIN_AA4 -to SDRAM_CASn
set_location_assignment PIN_AA10 -to SDRAM_DQ[0]
set_location_assignment PIN_AB9 -to SDRAM_DQ[1]
set_location_assignment PIN_AA9 -to SDRAM_DQ[2]
set_location_assignment PIN_AB8 -to SDRAM_DQ[3]
set_location_assignment PIN_AA8 -to SDRAM_DQ[4]
set_location_assignment PIN_AB7 -to SDRAM_DQ[5]
set_location_assignment PIN_AA7 -to SDRAM_DQ[6]
set_location_assignment PIN_AB5 -to SDRAM_DQ[7]
set_location_assignment PIN_Y7 -to SDRAM_DQ[8]
set_location_assignment PIN_W8 -to SDRAM_DQ[9]
set_location_assignment PIN_Y8 -to SDRAM_DQ[10]
set_location_assignment PIN_V9 -to SDRAM_DQ[11]
set_location_assignment PIN_V10 -to SDRAM_DQ[12]
set_location_assignment PIN_Y10 -to SDRAM_DQ[13]
set_location_assignment PIN_W10 -to SDRAM_DQ[14]
set_location_assignment PIN_V11 -to SDRAM_DQ[15]
set_location_assignment PIN_Y1 -to SDRAM_BA[0]
set_location_assignment PIN_W2 -to SDRAM_BA[1]
set_location_assignment PIN_V2 -to SDRAM_A[0]
set_location_assignment PIN_V1 -to SDRAM_A[1]
set_location_assignment PIN_U2 -to SDRAM_A[2]
set_location_assignment PIN_U1 -to SDRAM_A[3]
set_location_assignment PIN_V3 -to SDRAM_A[4]
set_location_assignment PIN_V4 -to SDRAM_A[5]
set_location_assignment PIN_Y2 -to SDRAM_A[6]
set_location_assignment PIN_AA1 -to SDRAM_A[7]
set_location_assignment PIN_Y3 -to SDRAM_A[8]
set_location_assignment PIN_V5 -to SDRAM_A[9]
set_location_assignment PIN_W1 -to SDRAM_A[10]
set_location_assignment PIN_Y4 -to SDRAM_A[11]
set_location_assignment PIN_V6 -to SDRAM_A[12]
set_location_assignment PIN_B17 -to UART0_dtr
set_location_assignment PIN_B15 -to UART0_out
set_location_assignment PIN_B16 -to UART0_in
set_location_assignment PIN_C3 -to UART2_out
set_location_assignment PIN_A5 -to UART2_in
set_location_assignment PIN_B10 -to SPI0_clk
set_location_assignment PIN_A15 -to SPI0_cs
set_location_assignment PIN_B9 -to SPI0_data
set_location_assignment PIN_B13 -to SPI0_q
set_location_assignment PIN_B14 -to SPI0_wp
set_location_assignment PIN_B8 -to SPI0_hold
set_location_assignment PIN_R2 -to SPI1_clk
set_location_assignment PIN_R1 -to SPI1_cs
set_location_assignment PIN_N1 -to SPI1_mosi
set_location_assignment PIN_N2 -to SPI1_miso
set_location_assignment PIN_P1 -to SPI1_rst
set_location_assignment PIN_P2 -to SPI1_nint
set_location_assignment PIN_D2 -to SPI2_clk
set_location_assignment PIN_M1 -to SPI2_cs
set_location_assignment PIN_F2 -to SPI2_mosi
set_location_assignment PIN_E1 -to SPI2_miso
set_location_assignment PIN_H1 -to SPI2_rst
set_location_assignment PIN_F1 -to SPI2_nint
set_location_assignment PIN_A3 -to PS2_data
set_location_assignment PIN_B2 -to PS2_clk
set_location_assignment PIN_A19 -to SPI3_cs
set_location_assignment PIN_B20 -to SPI3_clk
set_location_assignment PIN_A20 -to SPI3_mosi
set_location_assignment PIN_B18 -to SPI3_miso
set_location_assignment PIN_A18 -to SPI3_nrst
set_location_assignment PIN_B19 -to SPI3_int
set_location_assignment PIN_AA14 -to SPI4_cs
set_location_assignment PIN_AA15 -to SPI4_clk
set_location_assignment PIN_AA16 -to SPI4_mosi
set_location_assignment PIN_AA17 -to SPI4_miso
set_location_assignment PIN_AA13 -to SPI4_gp
set_location_assignment PIN_R22 -to GPI[0]
set_location_assignment PIN_U22 -to GPI[1]
set_location_assignment PIN_V22 -to GPI[2]
set_location_assignment PIN_W22 -to GPI[3]
set_location_assignment PIN_Y22 -to GPO[0]
set_location_assignment PIN_AA20 -to GPO[1]
set_location_assignment PIN_AA19 -to GPO[2]
set_location_assignment PIN_AA18 -to GPO[3]
set_location_assignment PIN_C2 -to DIPS[0]
set_location_assignment PIN_H2 -to DIPS[1]
set_location_assignment PIN_J2 -to DIPS[2]
set_location_assignment PIN_M2 -to DIPS[3]
set_location_assignment PIN_B22 -to TMDS_p[3]
set_location_assignment PIN_B21 -to TMDS_n[3]
set_location_assignment PIN_E22 -to TMDS_p[2]
set_location_assignment PIN_E21 -to TMDS_n[2]
set_location_assignment PIN_D22 -to TMDS_p[1]
set_location_assignment PIN_D21 -to TMDS_n[1]
set_location_assignment PIN_C22 -to TMDS_p[0]
set_location_assignment PIN_C21 -to TMDS_n[0]
set_location_assignment PIN_C1 -to led_Booted
set_location_assignment PIN_AB17 -to led_Eth
set_location_assignment PIN_AB19 -to led_Flash
set_location_assignment PIN_B1 -to led_USB0
set_location_assignment PIN_AB20 -to led_USB1
set_location_assignment PIN_AB13 -to led_PS2
set_location_assignment PIN_AB16 -to led_HDMI
set_location_assignment PIN_AB18 -to led_QSPI
set_location_assignment PIN_AB15 -to led_GPU
set_location_assignment PIN_AB14 -to led_I2S
set_location_assignment PIN_B6 -to I2S_SDIN
set_location_assignment PIN_B5 -to I2S_SCLK
set_location_assignment PIN_C4 -to I2S_LRCLK
set_location_assignment PIN_B4 -to I2S_MCLK
set_location_assignment PIN_Y21 -to composite[0]
set_location_assignment PIN_W21 -to composite[1]
set_location_assignment PIN_V21 -to composite[2]
set_location_assignment PIN_U21 -to composite[3]
set_location_assignment PIN_R21 -to composite[4]
set_location_assignment PIN_P21 -to composite[5]
set_location_assignment PIN_N21 -to composite[6]
set_location_assignment PIN_M21 -to composite[7]
set_instance_assignment -name IO_STANDARD LVDS -to TMDS_p[3]
set_instance_assignment -name IO_STANDARD LVDS -to TMDS_n[3]
set_instance_assignment -name IO_STANDARD LVDS -to TMDS_p[2]
set_instance_assignment -name IO_STANDARD LVDS -to TMDS_n[2]
set_instance_assignment -name IO_STANDARD LVDS -to TMDS_p[1]
set_instance_assignment -name IO_STANDARD LVDS -to TMDS_n[1]
set_instance_assignment -name IO_STANDARD LVDS -to TMDS_p[0]
set_instance_assignment -name IO_STANDARD LVDS -to TMDS_n[0]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to GPI[0]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to GPI[1]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to GPI[2]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to GPI[3]
set_global_assignment -name IOBANK_VCCIO 2.5V -section_id 6
set_global_assignment -name OPTIMIZATION_MODE BALANCED
set_location_assignment PIN_Y13 -to nBtnl
set_location_assignment PIN_W13 -to nBtnr
set_global_assignment -name VERILOG_FILE modules/FPGC5.v
set_global_assignment -name VERILOG_FILE modules/GPU/NTSC/RGBtoYPhaseAmpl.v
set_global_assignment -name VERILOG_FILE modules/GPU/NTSC/RGB332toNTSC.v
set_global_assignment -name VERILOG_FILE modules/GPU/NTSC/PhaseGen.v
set_global_assignment -name VERILOG_FILE modules/GPU/NTSC/NTSC.v
set_global_assignment -name QIP_FILE clkMux/synthesis/clkMux.qip
set_global_assignment -name VERILOG_FILE modules/GPU/FSX.v
set_global_assignment -name VERILOG_FILE modules/GPU/HDMI/TMDSenc.v
set_global_assignment -name VERILOG_FILE modules/GPU/HDMI/RGB2HDMI.v
set_global_assignment -name VERILOG_FILE modules/GPU/TimingGenerator.v
set_global_assignment -name VERILOG_FILE modules/GPU/BGWrenderer.v
set_global_assignment -name VERILOG_FILE modules/IO/LEDvisualizer.v
set_global_assignment -name VERILOG_FILE modules/IO/SimpleSPI.v
set_global_assignment -name VERILOG_FILE modules/IO/UARTrx.v
set_global_assignment -name VERILOG_FILE modules/IO/UARTtx.v
set_global_assignment -name VERILOG_FILE modules/IO/OStimer.v
set_global_assignment -name VERILOG_FILE modules/IO/NESpadReader.v
set_global_assignment -name VERILOG_FILE modules/IO/Keyboard.v
set_global_assignment -name VERILOG_FILE modules/CPU/ALU.v
set_global_assignment -name VERILOG_FILE modules/CPU/Arbiter.v
set_global_assignment -name VERILOG_FILE modules/CPU/ControlUnit.v
set_global_assignment -name VERILOG_FILE modules/CPU/CPU.v
set_global_assignment -name VERILOG_FILE modules/CPU/DataMem.v
set_global_assignment -name VERILOG_FILE modules/CPU/InstrMem.v
set_global_assignment -name VERILOG_FILE modules/CPU/InstructionDecoder.v
set_global_assignment -name VERILOG_FILE modules/CPU/Regbank.v
set_global_assignment -name VERILOG_FILE modules/CPU/Regr.v
set_global_assignment -name VERILOG_FILE modules/CPU/Stack.v
set_global_assignment -name VERILOG_FILE modules/CPU/IntController.v
set_global_assignment -name VERILOG_FILE modules/Memory/VRAM.v
set_global_assignment -name VERILOG_FILE modules/Memory/SPIreader.v
set_global_assignment -name VERILOG_FILE modules/Memory/SDRAMcontroller.v
set_global_assignment -name VERILOG_FILE modules/Memory/ROM.v
set_global_assignment -name VERILOG_FILE modules/Memory/MemoryUnit.v
set_global_assignment -name VERILOG_FILE modules/MultiStabilizer.v
set_global_assignment -name VERILOG_FILE modules/DtrReset.v
set_global_assignment -name QIP_FILE clock_pll.qip
set_global_assignment -name QIP_FILE lvds.qip
set_global_assignment -name QIP_FILE ddr.qip
set_global_assignment -name SDC_FILE FPGC5.sdc
set_global_assignment -name QIP_FILE NTSC_pll.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top