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Assembler
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7e81e7fa17
Added files missing from last commit (L1I cache).
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1 year ago |
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BCC
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add43b75da
L2 cache at 100MHz now greatly increases performance. Attempted to create l1i and l1d cache, but becomes unstable and the issue is difficult to similate/replicate. Therefore, all l1 cache is now bypassed and the code can be found in l1cacheUnstable.v. As no l1 cache anymore, I removed some ccache statements to increase performance as this instruction currently does nothing.
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1 year ago |
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Documentation
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7e81e7fa17
Added files missing from last commit (L1I cache).
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1 year ago |
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Graphics
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c4599a63cc
New documentation structure. Updated some documentation. Added relevant graphics scripts and files from FPGC5 repo.
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2 years ago |
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Programmer
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5af536210d
Fixed instability by adding clear cache instruction during SPI transfer. No idea why this fixed the issue, as the I/O address range is above the limit for cache to work.
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1 year ago |
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Quartus
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88681ec5d0
New arbiter that further improves performance by removing latency for instruction memory access. Created instability again, which I found to be caused by bad interrupt timings. Fixed by changing the interruptValid wire to use branch_MEM for alignment. I do not know why this fixed all problems as it is very hard to simulate this issue. L1 cache should be possible again!
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1 year ago |
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SublimeText3
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1026f4776c
Cleaned up some files
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2 years ago |
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Verilog
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88681ec5d0
New arbiter that further improves performance by removing latency for instruction memory access. Created instability again, which I found to be caused by bad interrupt timings. Fixed by changing the interruptValid wire to use branch_MEM for alignment. I do not know why this fixed all problems as it is very hard to simulate this issue. L1 cache should be possible again!
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1 year ago |
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.gitattributes
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b9bc26129d
Added gitattributes to ignore the huge UARTbootloader.asm file. Deleted old quartus test project.
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2 years ago |
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.gitignore
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a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
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2 years ago |
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LICENSE.txt
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9ec3298860
Updated README and added licence so repo can go public now
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2 years ago |
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README.md
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3d9b4194f7
Added initial documentation
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2 years ago |
bart
88681ec5d0
New arbiter that further improves performance by removing latency for instruction memory access. Created instability again, which I found to be caused by bad interrupt timings. Fixed by changing the interruptValid wire to use branch_MEM for alignment. I do not know why this fixed all problems as it is very hard to simulate this issue. L1 cache should be possible again!
