| .. |
|
CPU
|
3af9eecaa9
Added signed fixed point multiplication to ALU.
|
1 ano atrás |
|
GPU
|
0fd222280a
Added halfres rendering mode to gpu and mu. Added millis counter to mu. Raycaster now renders at half resolution and many improvements. Now at 40 to 70fps.
|
1 ano atrás |
|
IO
|
0fd222280a
Added halfres rendering mode to gpu and mu. Added millis counter to mu. Raycaster now renders at half resolution and many improvements. Now at 40 to 70fps.
|
1 ano atrás |
|
Memory
|
0fd222280a
Added halfres rendering mode to gpu and mu. Added millis counter to mu. Raycaster now renders at half resolution and many improvements. Now at 40 to 70fps.
|
1 ano atrás |
|
DtrReset.v
|
b74702c915
Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram
|
2 anos atrás |
|
FPGC6.v
|
0fd222280a
Added halfres rendering mode to gpu and mu. Added millis counter to mu. Raycaster now renders at half resolution and many improvements. Now at 40 to 70fps.
|
1 ano atrás |
|
MultiStabilizer.v
|
b74702c915
Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram
|
2 anos atrás |
bart
0fd222280a
Added halfres rendering mode to gpu and mu. Added millis counter to mu. Raycaster now renders at half resolution and many improvements. Now at 40 to 70fps.