vcsmx_setup.sh 9.4 KB

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  1. # (C) 2001-2023 Altera Corporation. All rights reserved.
  2. # Your use of Altera Corporation's design tools, logic functions and
  3. # other software and tools, and its AMPP partner logic functions, and
  4. # any output files any of the foregoing (including device programming
  5. # or simulation files), and any associated documentation or information
  6. # are expressly subject to the terms and conditions of the Altera
  7. # Program License Subscription Agreement, Altera MegaCore Function
  8. # License Agreement, or other applicable license agreement, including,
  9. # without limitation, that your use is for the sole purpose of
  10. # programming logic devices manufactured by Altera and sold by Altera
  11. # or its authorized distributors. Please refer to the applicable
  12. # agreement for further details.
  13. # ACDS 21.1 850 linux 2023.09.03.15:07:27
  14. # ----------------------------------------
  15. # vcsmx - auto-generated simulation script
  16. # ----------------------------------------
  17. # This script provides commands to simulate the following IP detected in
  18. # your Quartus project:
  19. # mainpll
  20. #
  21. # Altera recommends that you source this Quartus-generated IP simulation
  22. # script from your own customized top-level script, and avoid editing this
  23. # generated script.
  24. #
  25. # To write a top-level shell script that compiles Altera simulation libraries
  26. # and the Quartus-generated IP in your project, along with your design and
  27. # testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
  28. # into a new file, e.g. named "vcsmx_sim.sh", and modify text as directed.
  29. #
  30. # You can also modify the simulation flow to suit your needs. Set the
  31. # following variables to 1 to disable their corresponding processes:
  32. # - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
  33. # - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
  34. # - SKIP_COM: skip compiling Quartus-generated IP simulation files
  35. # - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
  36. #
  37. # ----------------------------------------
  38. # # TOP-LEVEL TEMPLATE - BEGIN
  39. # #
  40. # # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
  41. # # construct paths to the files required to simulate the IP in your Quartus
  42. # # project. By default, the IP script assumes that you are launching the
  43. # # simulator from the IP script location. If launching from another
  44. # # location, set QSYS_SIMDIR to the output directory you specified when you
  45. # # generated the IP script, relative to the directory from which you launch
  46. # # the simulator. In this case, you must also copy the generated library
  47. # # setup "synopsys_sim.setup" into the location from which you launch the
  48. # # simulator, or incorporate into any existing library setup.
  49. # #
  50. # # Run Quartus-generated IP simulation script once to compile Quartus EDA
  51. # # simulation libraries and Quartus-generated IP simulation files, and copy
  52. # # any ROM/RAM initialization files to the simulation directory.
  53. # #
  54. # # - If necessary, specify any compilation options:
  55. # # USER_DEFINED_COMPILE_OPTIONS
  56. # # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
  57. # # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
  58. # #
  59. # source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
  60. # SKIP_ELAB=1 \
  61. # SKIP_SIM=1 \
  62. # USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
  63. # USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
  64. # USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
  65. # QSYS_SIMDIR=<script generation output directory>
  66. # #
  67. # # Compile all design files and testbench files, including the top level.
  68. # # (These are all the files required for simulation other than the files
  69. # # compiled by the IP script)
  70. # #
  71. # vlogan <compilation options> <design and testbench files>
  72. # #
  73. # # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
  74. # # testbench module/entity name.
  75. # #
  76. # # Run the IP script again to elaborate and simulate the top level:
  77. # # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
  78. # # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
  79. # # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
  80. # #
  81. # source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
  82. # SKIP_FILE_COPY=1 \
  83. # SKIP_DEV_COM=1 \
  84. # SKIP_COM=1 \
  85. # TOP_LEVEL_NAME="'-top <simulation top>'" \
  86. # QSYS_SIMDIR=<script generation output directory> \
  87. # USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
  88. # USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
  89. # #
  90. # # TOP-LEVEL TEMPLATE - END
  91. # ----------------------------------------
  92. #
  93. # IP SIMULATION SCRIPT
  94. # ----------------------------------------
  95. # If mainpll is one of several IP cores in your
  96. # Quartus project, you can generate a simulation script
  97. # suitable for inclusion in your top-level simulation
  98. # script by running the following command line:
  99. #
  100. # ip-setup-simulation --quartus-project=<quartus project>
  101. #
  102. # ip-setup-simulation will discover the Altera IP
  103. # within the Quartus project, and generate a unified
  104. # script which supports all the Altera IP within the design.
  105. # ----------------------------------------
  106. # ACDS 21.1 850 linux 2023.09.03.15:07:27
  107. # ----------------------------------------
  108. # initialize variables
  109. TOP_LEVEL_NAME="mainpll"
  110. QSYS_SIMDIR="./../../"
  111. QUARTUS_INSTALL_DIR="/home/bart/intelFPGA_lite/21.1/quartus/"
  112. SKIP_FILE_COPY=0
  113. SKIP_DEV_COM=0
  114. SKIP_COM=0
  115. SKIP_ELAB=0
  116. SKIP_SIM=0
  117. USER_DEFINED_ELAB_OPTIONS=""
  118. USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
  119. # ----------------------------------------
  120. # overwrite variables - DO NOT MODIFY!
  121. # This block evaluates each command line argument, typically used for
  122. # overwriting variables. An example usage:
  123. # sh <simulator>_setup.sh SKIP_SIM=1
  124. for expression in "$@"; do
  125. eval $expression
  126. if [ $? -ne 0 ]; then
  127. echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
  128. exit $?
  129. fi
  130. done
  131. # ----------------------------------------
  132. # initialize simulation properties - DO NOT MODIFY!
  133. ELAB_OPTIONS=""
  134. SIM_OPTIONS=""
  135. if [[ `vcs -platform` != *"amd64"* ]]; then
  136. :
  137. else
  138. :
  139. fi
  140. # ----------------------------------------
  141. # create compilation libraries
  142. mkdir -p ./libraries/work/
  143. mkdir -p ./libraries/altera_ver/
  144. mkdir -p ./libraries/lpm_ver/
  145. mkdir -p ./libraries/sgate_ver/
  146. mkdir -p ./libraries/altera_mf_ver/
  147. mkdir -p ./libraries/altera_lnsim_ver/
  148. mkdir -p ./libraries/cyclonev_ver/
  149. mkdir -p ./libraries/cyclonev_hssi_ver/
  150. mkdir -p ./libraries/cyclonev_pcie_hip_ver/
  151. # ----------------------------------------
  152. # copy RAM/ROM files to simulation directory
  153. # ----------------------------------------
  154. # compile device library files
  155. if [ $SKIP_DEV_COM -eq 0 ]; then
  156. vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
  157. vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
  158. vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
  159. vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
  160. vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
  161. vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v" -work cyclonev_ver
  162. vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hmi_atoms_ncrypt.v" -work cyclonev_ver
  163. vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v" -work cyclonev_ver
  164. vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi_ver
  165. vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v" -work cyclonev_hssi_ver
  166. vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
  167. vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v" -work cyclonev_pcie_hip_ver
  168. fi
  169. # ----------------------------------------
  170. # compile design files in correct order
  171. if [ $SKIP_COM -eq 0 ]; then
  172. vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/mainpll.vo"
  173. fi
  174. # ----------------------------------------
  175. # elaborate top level design
  176. if [ $SKIP_ELAB -eq 0 ]; then
  177. vcs -lca -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
  178. fi
  179. # ----------------------------------------
  180. # simulate
  181. if [ $SKIP_SIM -eq 0 ]; then
  182. ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
  183. fi