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CPU
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3af9eecaa9
Added signed fixed point multiplication to ALU.
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1 year ago |
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GPU
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4e7cdb1216
Changed pixelplane to 24 bit colors. Updated texture generator and raycaster to 24 bit color.
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1 year ago |
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IO
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69d109e653
Added hardware signed and unsigned integer division and modulo. Created simple integer calculator to test. Updated several programs and BDOS to use new division hardware while keeping software calculation as legacy functions.
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1 year ago |
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Memory
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4e7cdb1216
Changed pixelplane to 24 bit colors. Updated texture generator and raycaster to 24 bit color.
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1 year ago |
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DtrReset.v
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b74702c915
Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram
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2 years ago |
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FPGC6.v
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4e7cdb1216
Changed pixelplane to 24 bit colors. Updated texture generator and raycaster to 24 bit color.
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1 year ago |
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MultiStabilizer.v
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b74702c915
Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram
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2 years ago |
bart
4e7cdb1216
Changed pixelplane to 24 bit colors. Updated texture generator and raycaster to 24 bit color.