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FPGC_tb.v 8.3 KB

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  1. /*
  2. * Testbench
  3. * Simulates the entire FPGC
  4. */
  5. // Set timescale
  6. `timescale 1 ns/1 ns
  7. // tld
  8. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/FPGC6.v"
  9. // other logic
  10. `include "/home/bart/Documents/FPGA/FPGC5/Verilog/modules/MultiStabilizer.v"
  11. `include "/home/bart/Documents/FPGA/FPGC5/Verilog/modules/DtrReset.v"
  12. // cpu
  13. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/CPU.v"
  14. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/ALU.v"
  15. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/ControlUnit.v"
  16. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/InstructionDecoder.v"
  17. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/Regbank.v"
  18. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/Stack.v"
  19. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/InstrMem.v"
  20. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/DataMem.v"
  21. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/Regr.v"
  22. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/Arbiter.v"
  23. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/CPU/IntController.v"
  24. // memory
  25. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/Memory/VRAM.v"
  26. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/Memory/mt48lc16m16a2.v"
  27. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/Memory/w25q128jv.v"
  28. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/Memory/SDRAMcontroller.v"
  29. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/Memory/SPIreader.v"
  30. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/Memory/ROM.v"
  31. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/Memory/MemoryUnit.v"
  32. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/Memory/L2cache.v"
  33. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/Memory/L1Icache.v"
  34. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/Memory/L1Dcache.v"
  35. // io
  36. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/IO/Keyboard.v"
  37. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/IO/OStimer.v"
  38. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/IO/UARTtx.v"
  39. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/IO/UARTrx.v"
  40. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/IO/SimpleSPI.v"
  41. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/IO/LEDvisualizer.v"
  42. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/IO/FPDivider.v"
  43. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/IO/IDivider.v"
  44. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/IO/MillisCounter.v"
  45. // gpu
  46. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/FSX.v"
  47. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/BGWrenderer.v"
  48. //`include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/Spriterenderer.v"
  49. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/PixelEngine.v"
  50. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/TimingGenerator.v"
  51. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/HDMI/RGB2HDMI.v"
  52. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/HDMI/TMDSenc.v"
  53. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/HDMI/lvds.v"
  54. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/HDMI/ddr.v"
  55. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/NTSC/NTSC.v"
  56. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/NTSC/PhaseGen.v"
  57. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/NTSC/RGB332toNTSC.v"
  58. `include "/home/bart/Documents/FPGA/FPGC6/Verilog/modules/GPU/NTSC/RGBtoYPhaseAmpl.v"
  59. // Define testmodule
  60. module FPGC_tb;
  61. //Clock I/O
  62. reg clk;
  63. reg clk_SDRAM;
  64. reg nreset;
  65. //SPI0 Flash
  66. wire SPI0_clk;
  67. wire SPI0_cs;
  68. wire SPI0_data;
  69. wire SPI0_wp;
  70. wire SPI0_q;
  71. wire SPI0_hold;
  72. W25Q128JV spiFlash (
  73. .CLK (SPI0_clk),
  74. .DIO (SPI0_data),
  75. .CSn (SPI0_cs),
  76. .WPn (SPI0_wp),
  77. .HOLDn (SPI0_hold),
  78. .DO (SPI0_q)
  79. );
  80. //SDRAM
  81. wire SDRAM_CLK; // SDRAM clock
  82. wire [31 : 0] SDRAM_DQ; // SDRAM I/O
  83. wire [12 : 0] SDRAM_A; // SDRAM Address
  84. wire [1 : 0] SDRAM_BA; // Bank Address
  85. wire SDRAM_CKE; // Synchronous Clock Enable
  86. wire SDRAM_CSn; // CS#
  87. wire SDRAM_RASn; // RAS#
  88. wire SDRAM_CASn; // CAS#
  89. wire SDRAM_WEn; // WE#
  90. wire [3 : 0] SDRAM_DQM; // Mask
  91. assign SDRAM_CLK = clk_SDRAM;
  92. mt48lc16m16a2 sdram1 (
  93. .Dq (SDRAM_DQ[15:0]),
  94. .Addr (SDRAM_A),
  95. .Ba (SDRAM_BA),
  96. .Clk (SDRAM_CLK),
  97. .Cke (SDRAM_CKE),
  98. .Cs_n (SDRAM_CSn),
  99. .Ras_n (SDRAM_RASn),
  100. .Cas_n (SDRAM_CASn),
  101. .We_n (SDRAM_WEn),
  102. .Dqm (SDRAM_DQM[1:0])
  103. );
  104. mt48lc16m16a2 sdram2 (
  105. .Dq (SDRAM_DQ[31:16]),
  106. .Addr (SDRAM_A),
  107. .Ba (SDRAM_BA),
  108. .Clk (SDRAM_CLK),
  109. .Cke (SDRAM_CKE),
  110. .Cs_n (SDRAM_CSn),
  111. .Ras_n (SDRAM_RASn),
  112. .Cas_n (SDRAM_CASn),
  113. .We_n (SDRAM_WEn),
  114. .Dqm (SDRAM_DQM[3:2])
  115. );
  116. //HDMI
  117. wire [3:0] TMDS_p;
  118. wire [3:0] TMDS_n;
  119. //SPI1
  120. wire SPI1_clk;
  121. wire SPI1_cs;
  122. wire SPI1_mosi;
  123. wire SPI1_miso;
  124. assign SPI1_miso = 1'b1;
  125. wire SPI1_rst;
  126. reg SPI1_nint;
  127. //SPI2
  128. wire SPI2_clk;
  129. wire SPI2_cs;
  130. wire SPI2_mosi;
  131. wire SPI2_miso;
  132. wire SPI2_rst;
  133. reg SPI2_nint;
  134. //SPI3
  135. wire SPI3_clk;
  136. wire SPI3_cs;
  137. wire SPI3_mosi;
  138. wire SPI3_miso;
  139. wire SPI3_nrst;
  140. reg SPI3_int;
  141. //SPI4
  142. wire SPI4_clk;
  143. wire SPI4_cs;
  144. wire SPI4_mosi;
  145. wire SPI4_miso;
  146. reg SPI4_gp;
  147. //UART0
  148. reg UART0_in;
  149. wire UART0_out;
  150. reg UART0_dtr;
  151. //UART1
  152. //reg UART1_in;
  153. //wire UART1_out;
  154. //UART2
  155. reg UART2_in;
  156. wire UART2_out;
  157. //PS/2
  158. reg PS2_clk;
  159. reg PS2_data;
  160. //Led
  161. wire led;
  162. //GPIO
  163. wire [3:0] GPO;
  164. reg [3:0] GPI;
  165. //DIP Switch
  166. reg [3:0] DIPS;
  167. FPGC6 fpgc (
  168. .clk(clk),
  169. .clk_SDRAM(clk_SDRAM),
  170. .nreset(nreset),
  171. //HDMI
  172. .TMDS_p(TMDS_p),
  173. .TMDS_n(TMDS_n),
  174. //SDRAM
  175. .SDRAM_CLK(SDRAM_CLK),
  176. .SDRAM_CSn(SDRAM_CSn),
  177. .SDRAM_WEn(SDRAM_WEn),
  178. .SDRAM_CASn(SDRAM_CASn),
  179. .SDRAM_RASn(SDRAM_RASn),
  180. .SDRAM_CKE(SDRAM_CKE),
  181. .SDRAM_A(SDRAM_A),
  182. .SDRAM_BA(SDRAM_BA),
  183. .SDRAM_DQM(SDRAM_DQM),
  184. .SDRAM_DQ(SDRAM_DQ),
  185. //SPI0 flash
  186. .SPI0_clk(SPI0_clk),
  187. .SPI0_cs(SPI0_cs),
  188. .SPI0_data(SPI0_data),
  189. .SPI0_q(SPI0_q),
  190. .SPI0_wp(SPI0_wp),
  191. .SPI0_hold(SPI0_hold),
  192. //SPI1 CH376 bottom
  193. .SPI1_clk(SPI1_clk),
  194. .SPI1_cs(SPI1_cs),
  195. .SPI1_mosi(SPI1_mosi),
  196. .SPI1_miso(SPI1_miso),
  197. .SPI1_nint(SPI1_nint),
  198. .SPI1_rst(SPI1_rst),
  199. //SPI2 CH376 top
  200. .SPI2_clk(SPI2_clk),
  201. .SPI2_cs(SPI2_cs),
  202. .SPI2_mosi(SPI2_mosi),
  203. .SPI2_miso(SPI2_miso),
  204. .SPI2_nint(SPI2_nint),
  205. .SPI2_rst(SPI2_rst),
  206. //SPI3 W5500
  207. .SPI3_clk(SPI3_clk),
  208. .SPI3_cs(SPI3_cs),
  209. .SPI3_mosi(SPI3_mosi),
  210. .SPI3_miso(SPI3_miso),
  211. .SPI3_int(SPI3_int),
  212. .SPI3_nrst(SPI3_nrst),
  213. //SPI4 GP
  214. .SPI4_clk(SPI4_clk),
  215. .SPI4_cs(SPI4_cs),
  216. .SPI4_mosi(SPI4_mosi),
  217. .SPI4_miso(SPI4_miso),
  218. .SPI4_gp(SPI4_gp),
  219. //UART0
  220. .UART0_in(UART0_in),
  221. .UART0_out(UART0_out),
  222. .UART0_dtr(UART0_dtr),
  223. //UART1
  224. //.UART1_in(UART1_in),
  225. //.UART1_out(UART1_out),
  226. //UART2
  227. .UART2_in(UART2_in),
  228. .UART2_out(UART2_out),
  229. //PS/2
  230. .PS2_clk(PS2_clk),
  231. .PS2_data(PS2_data),
  232. //Led for debugging
  233. .led(led),
  234. //GPIO
  235. .GPI(GPI),
  236. .GPO(GPO),
  237. //DIP switch
  238. .DIPS(DIPS)
  239. );
  240. initial
  241. begin
  242. //Dump everything for GTKwave
  243. $dumpfile("/home/bart/Documents/FPGA/FPGC6/Verilog/output/wave.vcd");
  244. $dumpvars;
  245. clk = 0;
  246. clk_SDRAM = 0;
  247. nreset = 1;
  248. SPI1_nint = 1;
  249. SPI2_nint = 1;
  250. SPI3_int = 0;
  251. SPI4_gp = 1;
  252. UART0_in = 1;
  253. UART0_dtr = 1;
  254. //UART1_in = 1;
  255. UART2_in = 1;
  256. PS2_clk = 1;
  257. PS2_data = 0;
  258. GPI = 4'b1111;
  259. DIPS = 4'b0000;
  260. DIPS[0] = 0; // spi = 0, uart = 1
  261. repeat(10)
  262. begin
  263. #5 clk_SDRAM = ~clk_SDRAM; clk = ~clk; //50MHz
  264. #5 clk_SDRAM = ~clk_SDRAM; //100MHz
  265. end
  266. nreset = 0;
  267. repeat(10)
  268. begin
  269. #5 clk_SDRAM = ~clk_SDRAM; clk = ~clk; //50MHz
  270. #5 clk_SDRAM = ~clk_SDRAM; //100MHz
  271. end
  272. nreset = 1;
  273. repeat(30000)
  274. begin
  275. #5 clk_SDRAM = ~clk_SDRAM; clk = ~clk; //50MHz
  276. #5 clk_SDRAM = ~clk_SDRAM; //100MHz
  277. end
  278. repeat(20000)
  279. begin
  280. #5 clk_SDRAM = ~clk_SDRAM; clk = ~clk; //50MHz
  281. #5 clk_SDRAM = ~clk_SDRAM; //100MHz
  282. end
  283. #1 $finish;
  284. end
  285. endmodule