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Assembler
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7e81e7fa17
Added files missing from last commit (L1I cache).
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1 an în urmă |
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BCC
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52f2819774
Removed leftover ccache instructions from debugging instability problems. Commented out required ccache instructions for when L1I cache returns in the future.
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1 an în urmă |
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Documentation
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9a285550c0
Updated documentation a bit, added newlines to BENCH, removed wrong comments from L2cache.v
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1 an în urmă |
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Graphics
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c4599a63cc
New documentation structure. Updated some documentation. Added relevant graphics scripts and files from FPGC5 repo.
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2 ani în urmă |
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Programmer
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52f2819774
Removed leftover ccache instructions from debugging instability problems. Commented out required ccache instructions for when L1I cache returns in the future.
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1 an în urmă |
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Quartus
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2fe0518bb3
Improved interrupt timing/alignment, fixing bug where interrupts are not allowed during the UART bootloader.
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1 an în urmă |
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SublimeText3
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1026f4776c
Cleaned up some files
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2 ani în urmă |
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Verilog
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2fe0518bb3
Improved interrupt timing/alignment, fixing bug where interrupts are not allowed during the UART bootloader.
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1 an în urmă |
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.gitattributes
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b9bc26129d
Added gitattributes to ignore the huge UARTbootloader.asm file. Deleted old quartus test project.
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2 ani în urmă |
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.gitignore
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a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
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2 ani în urmă |
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LICENSE.txt
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9ec3298860
Updated README and added licence so repo can go public now
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2 ani în urmă |
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README.md
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3d9b4194f7
Added initial documentation
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2 ani în urmă |
bart
2fe0518bb3
Improved interrupt timing/alignment, fixing bug where interrupts are not allowed during the UART bootloader.
