FPGC6/Verilog/output/FPGC.gtkw

[*]
[*] GTKWave Analyzer v3.3.107 (w)1999-2020 BSI
[*] Sun Aug 27 13:38:25 2023
[*]
[dumpfile] "/home/bart/Documents/FPGA/FPGC6/Verilog/output/wave.vcd"
[dumpfile_mtime] "Sun Aug 27 13:36:03 2023"
[dumpfile_size] 16357434
[savefile] "/home/bart/Documents/FPGA/FPGC6/Verilog/output/FPGC.gtkw"
[timestart] 204900
[size] 2560 1387
[pos] -1 -1
*-16.666576 525000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] FPGC_tb.
[treeopen] FPGC_tb.fpgc.
[treeopen] FPGC_tb.fpgc.cpu.
[treeopen] FPGC_tb.fpgc.cpu.arbiter.
[sst_width] 227
[signals_width] 713
[sst_expanded] 1
[sst_vpaned_height] 985
@28
FPGC_tb.fpgc.clk
@22
FPGC_tb.fpgc.cpu.PC[26:0]
@200
-
-
-Arbiter
-
@22
FPGC_tb.fpgc.cpu.arbiter.addr_a[31:0]
FPGC_tb.fpgc.cpu.arbiter.data_a[31:0]
@28
FPGC_tb.fpgc.cpu.arbiter.we_a
FPGC_tb.fpgc.cpu.arbiter.start_a
FPGC_tb.fpgc.cpu.arbiter.done_a
@22
FPGC_tb.fpgc.cpu.arbiter.q[31:0]
@200
-
-
@22
FPGC_tb.fpgc.cpu.arbiter.addr_b[31:0]
FPGC_tb.fpgc.cpu.arbiter.data_b[31:0]
@28
FPGC_tb.fpgc.cpu.arbiter.we_b
FPGC_tb.fpgc.cpu.arbiter.start_b
FPGC_tb.fpgc.cpu.arbiter.done_b
@22
FPGC_tb.fpgc.cpu.arbiter.q[31:0]
@200
-
@201
-
@22
FPGC_tb.fpgc.cpu.arbiter.bus_addr[26:0]
FPGC_tb.fpgc.cpu.arbiter.bus_data[31:0]
@28
FPGC_tb.fpgc.cpu.arbiter.bus_we
FPGC_tb.fpgc.cpu.arbiter.bus_start
FPGC_tb.fpgc.cpu.arbiter.bus_done
@200
-
-
@24
FPGC_tb.fpgc.cpu.arbiter.state[2:0]
@200
-
-
-
-
-
-
@22
FPGC_tb.fpgc.cpu.arbiter_bus_addr[26:0]
FPGC_tb.fpgc.cpu.arbiter_bus_data[31:0]
@28
FPGC_tb.fpgc.cpu.arbiter_bus_start
FPGC_tb.fpgc.cpu.arbiter_bus_we
@22
FPGC_tb.fpgc.cpu.arbiter_bus_q[31:0]
@28
FPGC_tb.fpgc.cpu.arbiter_bus_done
@200
-
@22
FPGC_tb.fpgc.cpu.bus_addr[26:0]
FPGC_tb.fpgc.cpu.bus_data[31:0]
@28
FPGC_tb.fpgc.cpu.bus_we
FPGC_tb.fpgc.cpu.bus_start
@22
FPGC_tb.fpgc.cpu.bus_q[31:0]
@28
FPGC_tb.fpgc.cpu.bus_done
@200
-
@22
FPGC_tb.fpgc.cpu.sdc_addr[23:0]
FPGC_tb.fpgc.cpu.sdc_data[31:0]
@28
FPGC_tb.fpgc.cpu.sdc_we
FPGC_tb.fpgc.cpu.sdc_start
@22
FPGC_tb.fpgc.cpu.sdc_q[31:0]
@28
FPGC_tb.fpgc.cpu.sdc_done
@200
-
-SDRAMcontroller
@24
FPGC_tb.fpgc.sdramcontroller.sdc_addr[23:0]
@22
FPGC_tb.fpgc.sdramcontroller.sdc_data[31:0]
@28
FPGC_tb.fpgc.sdramcontroller.sdc_we
FPGC_tb.fpgc.sdramcontroller.sdc_start
FPGC_tb.fpgc.sdramcontroller.sdc_done
@24
FPGC_tb.fpgc.sdramcontroller.state[4:0]
@28
FPGC_tb.fpgc.sdramcontroller.is_refreshing
@22
FPGC_tb.fpgc.sdramcontroller.sdc_q[31:0]
@200
-
-
@22
FPGC_tb.fpgc.sdramcontroller.SDRAM_A[12:0]
@28
FPGC_tb.fpgc.sdramcontroller.SDRAM_BA[1:0]
FPGC_tb.fpgc.sdramcontroller.SDRAM_CASn
FPGC_tb.fpgc.sdramcontroller.SDRAM_CKE
@22
FPGC_tb.fpgc.sdramcontroller.SDRAM_CMD[3:0]
@28
FPGC_tb.fpgc.sdramcontroller.SDRAM_CSn
@22
FPGC_tb.fpgc.sdramcontroller.SDRAM_DATA[31:0]
FPGC_tb.fpgc.sdramcontroller.SDRAM_DQM[3:0]
FPGC_tb.fpgc.sdramcontroller.SDRAM_DQ[31:0]
@28
FPGC_tb.fpgc.sdramcontroller.SDRAM_DQ_OE
@22
FPGC_tb.fpgc.sdramcontroller.SDRAM_Q[31:0]
@28
FPGC_tb.fpgc.sdramcontroller.SDRAM_RASn
FPGC_tb.fpgc.sdramcontroller.SDRAM_WEn
@200
-
-SPI flash
@28
FPGC_tb.spiFlash.CLK
FPGC_tb.spiFlash.CSn
FPGC_tb.spiFlash.DIO
FPGC_tb.spiFlash.DO
FPGC_tb.spiFlash.HOLDn
FPGC_tb.spiFlash.WPn
@200
-
-
-MU
@22
FPGC_tb.fpgc.mu.bus_addr[26:0]
FPGC_tb.fpgc.mu.bus_d_reg[31:0]
FPGC_tb.fpgc.mu.bus_data[31:0]
@28
FPGC_tb.fpgc.mu.bus_done
FPGC_tb.fpgc.mu.bus_done_next
@22
FPGC_tb.fpgc.mu.bus_q[31:0]
FPGC_tb.fpgc.mu.bus_q_wire[31:0]
FPGC_tb.fpgc.mu.bus_q_wire_reg[31:0]
@28
FPGC_tb.fpgc.mu.bus_start
FPGC_tb.fpgc.mu.bus_we
@200
-
-
-Fetch
@28
FPGC_tb.fpgc.cpu.instr_DE[31:0]
@24
FPGC_tb.fpgc.cpu.pc_FE[31:0]
@28
FPGC_tb.fpgc.cpu.instr_hit_FE
@200
-
@28
FPGC_tb.fpgc.cpu.intDisabled
@22
FPGC_tb.fpgc.cpu.interruptValid
FPGC_tb.fpgc.cpu.pc_FE[31:0]
FPGC_tb.fpgc.cpu.pc_FE_backup[31:0]
FPGC_tb.fpgc.cpu.PC_backup_current[31:0]
@200
-
@28
FPGC_tb.fpgc.cpu.instr_MEM[31:0]
FPGC_tb.fpgc.cpu.jumpc_MEM
FPGC_tb.fpgc.cpu.branch_passed_MEM
@24
FPGC_tb.fpgc.cpu.jump_addr_MEM[31:0]
@200
-
@22
FPGC_tb.fpgc.mu.bus_addr[26:0]
@28
FPGC_tb.fpgc.mu.bus_start
@22
FPGC_tb.fpgc.mu.bus_q[31:0]
FPGC_tb.fpgc.mu.bus_q_wire[31:0]
@28
FPGC_tb.fpgc.mu.bus_done_next
@22
FPGC_tb.fpgc.mu.bus_q_wire_reg[31:0]
@28
FPGC_tb.fpgc.mu.bus_done
@22
FPGC_tb.fpgc.mu.UART0_rx.o_Rx_Byte[7:0]
@200
-
@22
FPGC_tb.DIPS[3:0]
@28
FPGC_tb.fpgc.cpu.intDisabled
FPGC_tb.fpgc.cpu.interruptValid
@200
-InstrMem
@28
FPGC_tb.fpgc.cpu.instrMem.clk
@200
-
@24
FPGC_tb.fpgc.cpu.instrMem.addr[31:0]
@22
FPGC_tb.fpgc.cpu.instrMem.q[31:0]
@28
FPGC_tb.fpgc.cpu.instrMem.ignoreNext
FPGC_tb.fpgc.cpu.instrMem.clear
FPGC_tb.fpgc.cpu.instrMem.hit
FPGC_tb.fpgc.cpu.instrMem.hold
@200
-
@22
FPGC_tb.fpgc.cpu.instrMem.bus_addr[31:0]
FPGC_tb.fpgc.cpu.instrMem.bus_data[31:0]
@28
FPGC_tb.fpgc.cpu.instrMem.bus_done
@22
FPGC_tb.fpgc.cpu.instrMem.bus_q[31:0]
@28
FPGC_tb.fpgc.cpu.instrMem.bus_start
FPGC_tb.fpgc.cpu.instrMem.bus_we
@200
-
-
@28
FPGC_tb.fpgc.cpu.clearCache_DE
FPGC_tb.fpgc.cpu.clearCache_EX
FPGC_tb.fpgc.cpu.clearCache_MEM
@200
-
-
-
-DataMem
@22
FPGC_tb.fpgc.cpu.dataMem.bus_addr[31:0]
FPGC_tb.fpgc.cpu.dataMem.bus_data[31:0]
FPGC_tb.fpgc.cpu.dataMem.bus_q[31:0]
@28
FPGC_tb.fpgc.cpu.dataMem.bus_we
FPGC_tb.fpgc.cpu.dataMem.bus_start
FPGC_tb.fpgc.cpu.dataMem.bus_done
@200
-
@24
FPGC_tb.fpgc.cpu.dataMem.bus_addr[31:0]
@28
FPGC_tb.fpgc.cpu.dataMem.busy
@22
FPGC_tb.fpgc.cpu.dataMem.qreg[31:0]
FPGC_tb.fpgc.cpu.dataMem.q[31:0]
@200
-
-
-
-
@28
FPGC_tb.fpgc.cpu.clearCache_DE
FPGC_tb.fpgc.cpu.clearCache_EX
FPGC_tb.fpgc.cpu.clearCache_MEM
@200
-
-L2Cache
-
-
-
-
[pattern_trace] 1
[pattern_trace] 0