bart 28bcde6466 New SDRAM controller that uses both SDRAM chips. Now separate bus from MU for better performance, as controller runs at 100MHz. Also updated some debug code as debugging was needed. Tested working in hardware. 2x performance boost in some cases. пре 1 година
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HDMI b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram пре 2 година
NTSC 1026f4776c Cleaned up some files пре 2 година
BGWrenderer.v b74702c915 Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram пре 2 година
FSX.v 28bcde6466 New SDRAM controller that uses both SDRAM chips. Now separate bus from MU for better performance, as controller runs at 100MHz. Also updated some debug code as debugging was needed. Tested working in hardware. 2x performance boost in some cases. пре 1 година
PixelEngine.v 6e3cd7cd9c PixelEngine now works in hardware with both HDMI and NTSC. Added pxtest and mandelbrot test programs. пре 2 година
TimingGenerator.v 7b14d2d273 Improved Pixel Engine. пре 2 година