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clock_pll_v_sim
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clock_pll_v.vo

clock_pll_v.vo 18 KB
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  1. //IP Functional Simulation Model
    2. 

  2. //VERSION_BEGIN 21.1 cbx_mgl 2022:06:23:22:26:17:SJ cbx_simgen 2022:06:23:22:02:32:SJ  VERSION_END
    3. 

  3. // synthesis VERILOG_INPUT_VERSION VERILOG_2001
    4. 

  4. // altera message_off 10463
    5. 

  5. 

  6. 

  7. 

  8. // Copyright (C) 2022  Intel Corporation. All rights reserved.
    9. 

  9. // Your use of Intel Corporation's design tools, logic functions 
    10. 

  10. // and other software and tools, and any partner logic 
    11. 

  11. // functions, and any output files from any of the foregoing 
    12. 

  12. // (including device programming or simulation files), and any 
    13. 

  13. // associated documentation or information are expressly subject 
    14. 

  14. // to the terms and conditions of the Intel Program License 
    15. 

  15. // Subscription Agreement, the Intel Quartus Prime License Agreement,
    16. 

  16. // the Intel FPGA IP License Agreement, or other applicable license
    17. 

  17. // agreement, including, without limitation, that your use is for
    18. 

  18. // the sole purpose of programming logic devices manufactured by
    19. 

  19. // Intel and sold by Intel or its authorized distributors.  Please
    20. 

  20. // refer to the applicable agreement for further details, at
    21. 

  21. // https://fpgasoftware.intel.com/eula.
    22. 

  22. 

  23. // You may only use these simulation model output files for simulation
    24. 

  24. // purposes and expressly not for synthesis or any other purposes (in which
    25. 

  25. // event Intel disclaims all warranties of any kind).
    26. 

  26. 

  27. 

  28. //synopsys translate_off
    29. 

  29. 

  30. //synthesis_resources = altera_pll 1 
    31. 

  31. `timescale 1 ps / 1 ps
    32. 

  32. module  clock_pll_v
    33. 

  33. 	( 
    34. 

  34. 	locked,
    35. 

  35. 	outclk_0,
    36. 

  36. 	outclk_1,
    37. 

  37. 	outclk_2,
    38. 

  38. 	outclk_3,
    39. 

  39. 	outclk_4,
    40. 

  40. 	refclk,
    41. 

  41. 	rst) /* synthesis synthesis_clearbox=1 */;
    42. 

  42. 	output   locked;
    43. 

  43. 	output   outclk_0;
    44. 

  44. 	output   outclk_1;
    45. 

  45. 	output   outclk_2;
    46. 

  46. 	output   outclk_3;
    47. 

  47. 	output   outclk_4;
    48. 

  48. 	input   refclk;
    49. 

  49. 	input   rst;
    50. 

  50. 

  51. 	wire  wire_clock_pll_v_altera_pll_altera_pll_i_2475_locked;
    52. 

  52. 	wire  [4:0]   wire_clock_pll_v_altera_pll_altera_pll_i_2475_outclk;
    53. 

  53. 

  54. 	altera_pll   clock_pll_v_altera_pll_altera_pll_i_2475
    55. 

  55. 	( 
    56. 

  56. 	.fbclk(1'b0),
    57. 

  57. 	.locked(wire_clock_pll_v_altera_pll_altera_pll_i_2475_locked),
    58. 

  58. 	.outclk(wire_clock_pll_v_altera_pll_altera_pll_i_2475_outclk),
    59. 

  59. 	.refclk(refclk),
    60. 

  60. 	.rst(rst));
    61. 

  61. 	defparam
    62. 

  62. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en0 = "false",
    63. 

  63. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en1 = "false",
    64. 

  64. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en10 = "false",
    65. 

  65. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en11 = "false",
    66. 

  66. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en12 = "false",
    67. 

  67. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en13 = "false",
    68. 

  68. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en14 = "false",
    69. 

  69. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en15 = "false",
    70. 

  70. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en16 = "false",
    71. 

  71. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en17 = "false",
    72. 

  72. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en2 = "false",
    73. 

  73. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en3 = "false",
    74. 

  74. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en4 = "false",
    75. 

  75. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en5 = "false",
    76. 

  76. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en6 = "false",
    77. 

  77. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en7 = "false",
    78. 

  78. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en8 = "false",
    79. 

  79. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en9 = "false",
    80. 

  80. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div0 = 1,
    81. 

  81. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div1 = 1,
    82. 

  82. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div10 = 1,
    83. 

  83. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div11 = 1,
    84. 

  84. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div12 = 1,
    85. 

  85. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div13 = 1,
    86. 

  86. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div14 = 1,
    87. 

  87. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div15 = 1,
    88. 

  88. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div16 = 1,
    89. 

  89. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div17 = 1,
    90. 

  90. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div2 = 1,
    91. 

  91. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div3 = 1,
    92. 

  92. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div4 = 1,
    93. 

  93. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div5 = 1,
    94. 

  94. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div6 = 1,
    95. 

  95. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div7 = 1,
    96. 

  96. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div8 = 1,
    97. 

  97. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div9 = 1,
    98. 

  98. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src0 = "ph_mux_clk",
    99. 

  99. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src1 = "ph_mux_clk",
    100. 

  100. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src10 = "ph_mux_clk",
    101. 

  101. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src11 = "ph_mux_clk",
    102. 

  102. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src12 = "ph_mux_clk",
    103. 

  103. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src13 = "ph_mux_clk",
    104. 

  104. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src14 = "ph_mux_clk",
    105. 

  105. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src15 = "ph_mux_clk",
    106. 

  106. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src16 = "ph_mux_clk",
    107. 

  107. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src17 = "ph_mux_clk",
    108. 

  108. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src2 = "ph_mux_clk",
    109. 

  109. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src3 = "ph_mux_clk",
    110. 

  110. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src4 = "ph_mux_clk",
    111. 

  111. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src5 = "ph_mux_clk",
    112. 

  112. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src6 = "ph_mux_clk",
    113. 

  113. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src7 = "ph_mux_clk",
    114. 

  114. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src8 = "ph_mux_clk",
    115. 

  115. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src9 = "ph_mux_clk",
    116. 

  116. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div0 = 1,
    117. 

  117. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div1 = 1,
    118. 

  118. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div10 = 1,
    119. 

  119. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div11 = 1,
    120. 

  120. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div12 = 1,
    121. 

  121. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div13 = 1,
    122. 

  122. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div14 = 1,
    123. 

  123. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div15 = 1,
    124. 

  124. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div16 = 1,
    125. 

  125. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div17 = 1,
    126. 

  126. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div2 = 1,
    127. 

  127. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div3 = 1,
    128. 

  128. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div4 = 1,
    129. 

  129. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div5 = 1,
    130. 

  130. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div6 = 1,
    131. 

  131. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div7 = 1,
    132. 

  132. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div8 = 1,
    133. 

  133. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div9 = 1,
    134. 

  134. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en0 = "false",
    135. 

  135. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en1 = "false",
    136. 

  136. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en10 = "false",
    137. 

  137. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en11 = "false",
    138. 

  138. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en12 = "false",
    139. 

  139. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en13 = "false",
    140. 

  140. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en14 = "false",
    141. 

  141. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en15 = "false",
    142. 

  142. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en16 = "false",
    143. 

  143. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en17 = "false",
    144. 

  144. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en2 = "false",
    145. 

  145. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en3 = "false",
    146. 

  146. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en4 = "false",
    147. 

  147. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en5 = "false",
    148. 

  148. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en6 = "false",
    149. 

  149. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en7 = "false",
    150. 

  150. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en8 = "false",
    151. 

  151. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en9 = "false",
    152. 

  152. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst0 = 0,
    153. 

  153. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst1 = 0,
    154. 

  154. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst10 = 0,
    155. 

  155. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst11 = 0,
    156. 

  156. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst12 = 0,
    157. 

  157. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst13 = 0,
    158. 

  158. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst14 = 0,
    159. 

  159. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst15 = 0,
    160. 

  160. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst16 = 0,
    161. 

  161. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst17 = 0,
    162. 

  162. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst2 = 0,
    163. 

  163. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst3 = 0,
    164. 

  164. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst4 = 0,
    165. 

  165. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst5 = 0,
    166. 

  166. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst6 = 0,
    167. 

  167. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst7 = 0,
    168. 

  168. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst8 = 0,
    169. 

  169. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst9 = 0,
    170. 

  170. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst0 = 1,
    171. 

  171. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst1 = 1,
    172. 

  172. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst10 = 1,
    173. 

  173. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst11 = 1,
    174. 

  174. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst12 = 1,
    175. 

  175. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst13 = 1,
    176. 

  176. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst14 = 1,
    177. 

  177. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst15 = 1,
    178. 

  178. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst16 = 1,
    179. 

  179. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst17 = 1,
    180. 

  180. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst2 = 1,
    181. 

  181. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst3 = 1,
    182. 

  182. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst4 = 1,
    183. 

  183. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst5 = 1,
    184. 

  184. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst6 = 1,
    185. 

  185. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst7 = 1,
    186. 

  186. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst8 = 1,
    187. 

  187. 		clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst9 = 1,
    188. 

  188. 		clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_0 = "UNUSED",
    189. 

  189. 		clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_1 = "UNUSED",
    190. 

  190. 		clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_2 = "UNUSED",
    191. 

  191. 		clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_3 = "UNUSED",
    192. 

  192. 		clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_4 = "UNUSED",
    193. 

  193. 		clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_5 = "UNUSED",
    194. 

  194. 		clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_6 = "UNUSED",
    195. 

  195. 		clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_7 = "UNUSED",
    196. 

  196. 		clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_8 = "UNUSED",
    197. 

  197. 		clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_global_0 = "false",
    198. 

  198. 		clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_global_1 = "false",
    199. 

  199. 		clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_global_2 = "false",
    200. 

  200. 		clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_global_3 = "false",
    201. 

  201. 		clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_global_4 = "false",
    202. 

  202. 		clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_global_5 = "false",
    203. 

  203. 		clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_global_6 = "false",
    204. 

  204. 		clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_global_7 = "false",
    205. 

  205. 		clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_global_8 = "false",
    206. 

  206. 		clock_pll_v_altera_pll_altera_pll_i_2475.data_rate = 0,
    207. 

  207. 		clock_pll_v_altera_pll_altera_pll_i_2475.deserialization_factor = 4,
    208. 

  208. 		clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle0 = 50,
    209. 

  209. 		clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle1 = 50,
    210. 

  210. 		clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle10 = 50,
    211. 

  211. 		clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle11 = 50,
    212. 

  212. 		clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle12 = 50,
    213. 

  213. 		clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle13 = 50,
    214. 

  214. 		clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle14 = 50,
    215. 

  215. 		clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle15 = 50,
    216. 

  216. 		clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle16 = 50,
    217. 

  217. 		clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle17 = 50,
    218. 

  218. 		clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle2 = 50,
    219. 

  219. 		clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle3 = 50,
    220. 

  220. 		clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle4 = 50,
    221. 

  221. 		clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle5 = 50,
    222. 

  222. 		clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle6 = 50,
    223. 

  223. 		clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle7 = 50,
    224. 

  224. 		clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle8 = 50,
    225. 

  225. 		clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle9 = 50,
    226. 

  226. 		clock_pll_v_altera_pll_altera_pll_i_2475.fractional_vco_multiplier = "false",
    227. 

  227. 		clock_pll_v_altera_pll_altera_pll_i_2475.m_cnt_bypass_en = "false",
    228. 

  228. 		clock_pll_v_altera_pll_altera_pll_i_2475.m_cnt_hi_div = 1,
    229. 

  229. 		clock_pll_v_altera_pll_altera_pll_i_2475.m_cnt_lo_div = 1,
    230. 

  230. 		clock_pll_v_altera_pll_altera_pll_i_2475.m_cnt_odd_div_duty_en = "false",
    231. 

  231. 		clock_pll_v_altera_pll_altera_pll_i_2475.mimic_fbclk_type = "gclk",
    232. 

  232. 		clock_pll_v_altera_pll_altera_pll_i_2475.n_cnt_bypass_en = "false",
    233. 

  233. 		clock_pll_v_altera_pll_altera_pll_i_2475.n_cnt_hi_div = 1,
    234. 

  234. 		clock_pll_v_altera_pll_altera_pll_i_2475.n_cnt_lo_div = 1,
    235. 

  235. 		clock_pll_v_altera_pll_altera_pll_i_2475.n_cnt_odd_div_duty_en = "false",
    236. 

  236. 		clock_pll_v_altera_pll_altera_pll_i_2475.number_of_clocks = 5,
    237. 

  237. 		clock_pll_v_altera_pll_altera_pll_i_2475.operation_mode = "direct",
    238. 

  238. 		clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency0 = "25.000000 MHz",
    239. 

  239. 		clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency1 = "125.000000 MHz",
    240. 

  240. 		clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency10 = "0 MHz",
    241. 

  241. 		clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency11 = "0 MHz",
    242. 

  242. 		clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency12 = "0 MHz",
    243. 

  243. 		clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency13 = "0 MHz",
    244. 

  244. 		clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency14 = "0 MHz",
    245. 

  245. 		clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency15 = "0 MHz",
    246. 

  246. 		clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency16 = "0 MHz",
    247. 

  247. 		clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency17 = "0 MHz",
    248. 

  248. 		clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency2 = "100.000000 MHz",
    249. 

  249. 		clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency3 = "100.000000 MHz",
    250. 

  250. 		clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency4 = "50.000000 MHz",
    251. 

  251. 		clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency5 = "0 MHz",
    252. 

  252. 		clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency6 = "0 MHz",
    253. 

  253. 		clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency7 = "0 MHz",
    254. 

  254. 		clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency8 = "0 MHz",
    255. 

  255. 		clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency9 = "0 MHz",
    256. 

  256. 		clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift0 = "0 ps",
    257. 

  257. 		clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift1 = "0 ps",
    258. 

  258. 		clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift10 = "0 ps",
    259. 

  259. 		clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift11 = "0 ps",
    260. 

  260. 		clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift12 = "0 ps",
    261. 

  261. 		clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift13 = "0 ps",
    262. 

  262. 		clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift14 = "0 ps",
    263. 

  263. 		clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift15 = "0 ps",
    264. 

  264. 		clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift16 = "0 ps",
    265. 

  265. 		clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift17 = "0 ps",
    266. 

  266. 		clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift2 = "0 ps",
    267. 

  267. 		clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift3 = "2500 ps",
    268. 

  268. 		clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift4 = "0 ps",
    269. 

  269. 		clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift5 = "0 ps",
    270. 

  270. 		clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift6 = "0 ps",
    271. 

  271. 		clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift7 = "0 ps",
    272. 

  272. 		clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift8 = "0 ps",
    273. 

  273. 		clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift9 = "0 ps",
    274. 

  274. 		clock_pll_v_altera_pll_altera_pll_i_2475.pll_auto_clk_sw_en = "false",
    275. 

  275. 		clock_pll_v_altera_pll_altera_pll_i_2475.pll_bw_sel = "low",
    276. 

  276. 		clock_pll_v_altera_pll_altera_pll_i_2475.pll_bwctrl = 0,
    277. 

  277. 		clock_pll_v_altera_pll_altera_pll_i_2475.pll_clk_loss_sw_en = "false",
    278. 

  278. 		clock_pll_v_altera_pll_altera_pll_i_2475.pll_clk_sw_dly = 0,
    279. 

  279. 		clock_pll_v_altera_pll_altera_pll_i_2475.pll_clkin_0_src = "clk_0",
    280. 

  280. 		clock_pll_v_altera_pll_altera_pll_i_2475.pll_clkin_1_src = "clk_0",
    281. 

  281. 		clock_pll_v_altera_pll_altera_pll_i_2475.pll_cp_current = 0,
    282. 

  282. 		clock_pll_v_altera_pll_altera_pll_i_2475.pll_dsm_out_sel = "1st_order",
    283. 

  283. 		clock_pll_v_altera_pll_altera_pll_i_2475.pll_extclk_0_cnt_src = "pll_extclk_cnt_src_vss",
    284. 

  284. 		clock_pll_v_altera_pll_altera_pll_i_2475.pll_extclk_1_cnt_src = "pll_extclk_cnt_src_vss",
    285. 

  285. 		clock_pll_v_altera_pll_altera_pll_i_2475.pll_fbclk_mux_1 = "glb",
    286. 

  286. 		clock_pll_v_altera_pll_altera_pll_i_2475.pll_fbclk_mux_2 = "fb_1",
    287. 

  287. 		clock_pll_v_altera_pll_altera_pll_i_2475.pll_fractional_cout = 24,
    288. 

  288. 		clock_pll_v_altera_pll_altera_pll_i_2475.pll_fractional_division = 1,
    289. 

  289. 		clock_pll_v_altera_pll_altera_pll_i_2475.pll_m_cnt_in_src = "ph_mux_clk",
    290. 

  290. 		clock_pll_v_altera_pll_altera_pll_i_2475.pll_manu_clk_sw_en = "false",
    291. 

  291. 		clock_pll_v_altera_pll_altera_pll_i_2475.pll_output_clk_frequency = "0 MHz",
    292. 

  292. 		clock_pll_v_altera_pll_altera_pll_i_2475.pll_slf_rst = "false",
    293. 

  293. 		clock_pll_v_altera_pll_altera_pll_i_2475.pll_subtype = "General",
    294. 

  294. 		clock_pll_v_altera_pll_altera_pll_i_2475.pll_type = "General",
    295. 

  295. 		clock_pll_v_altera_pll_altera_pll_i_2475.pll_vco_div = 1,
    296. 

  296. 		clock_pll_v_altera_pll_altera_pll_i_2475.pll_vcoph_div = 1,
    297. 

  297. 		clock_pll_v_altera_pll_altera_pll_i_2475.refclk1_frequency = "0 MHz",
    298. 

  298. 		clock_pll_v_altera_pll_altera_pll_i_2475.reference_clock_frequency = "50.0 MHz",
    299. 

  299. 		clock_pll_v_altera_pll_altera_pll_i_2475.sim_additional_refclk_cycles_to_lock = 0;
    300. 

  300. 	assign
    301. 

  301. 		locked = wire_clock_pll_v_altera_pll_altera_pll_i_2475_locked,
    302. 

  302. 		outclk_0 = wire_clock_pll_v_altera_pll_altera_pll_i_2475_outclk[0],
    303. 

  303. 		outclk_1 = wire_clock_pll_v_altera_pll_altera_pll_i_2475_outclk[1],
    304. 

  304. 		outclk_2 = wire_clock_pll_v_altera_pll_altera_pll_i_2475_outclk[2],
    305. 

  305. 		outclk_3 = wire_clock_pll_v_altera_pll_altera_pll_i_2475_outclk[3],
    306. 

  306. 		outclk_4 = wire_clock_pll_v_altera_pll_altera_pll_i_2475_outclk[4];
    307. 

  307. endmodule //clock_pll_v
    308. 

  308. //synopsys translate_on
    309. 

  309. //VALID FILE
    310.