FPGC6/Quartus/clock_pll_v.spd

<?xml version="1.0" encoding="UTF-8"?>
<simPackage>
 <file path="clock_pll_v_sim/clock_pll_v.vo" type="VERILOG" />
 <topLevel name="clock_pll_v" />
 <deviceFamily name="cyclonev" />
</simPackage>