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bart
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FPGC6
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https://github.com/bartpleiter/FPGC6
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EP4CE15
cpu100mhz
fast-cpu-pipeline
main
FPGC6
/
Quartus
/
output_files
bart
2fe0518bb3
Improved interrupt timing/alignment, fixing bug where interrupts are not allowed during the UART bootloader.
1 ano atrás
..
output_file.jic
2fe0518bb3
Improved interrupt timing/alignment, fixing bug where interrupts are not allowed during the UART bootloader.
1 ano atrás