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bart
/
FPGC6
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https://github.com/bartpleiter/FPGC6
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EP4CE15
cpu100mhz
fast-cpu-pipeline
main
FPGC6
/
Quartus
/
clock_pll_v
bart
a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
2 anos atrás
..
clock_pll_v_0002.qip
a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
2 anos atrás
clock_pll_v_0002.v
a76905443f
Ported Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
2 anos atrás