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B32P_tb.v
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b6831c4209
Added L2 cache (no L1 for now) between CPU and SDRAM controller. No noticable performance difference, can likely be optimized further to reduce cache hit latency.
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1 year ago |
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FPGC_100MHz_tb.v
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9438941e15
Initial setup to simulate 100mhz cpu in verilog testbench.
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6 months ago |
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FPGC_tb.v
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c1486c43e0
Documentation update. Remove subl3 files.
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6 months ago |
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FSX_tb.v
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6e3cd7cd9c
PixelEngine now works in hardware with both HDMI and NTSC. Added pxtest and mandelbrot test programs.
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2 years ago |
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SDRAM_tb.v
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28bcde6466
New SDRAM controller that uses both SDRAM chips. Now separate bus from MU for better performance, as controller runs at 100MHz. Also updated some debug code as debugging was needed. Tested working in hardware. 2x performance boost in some cases.
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1 year ago |
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divider_tb.v
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69d109e653
Added hardware signed and unsigned integer division and modulo. Created simple integer calculator to test. Updated several programs and BDOS to use new division hardware while keeping software calculation as legacy functions.
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1 year ago |
bartpleiter
9438941e15
Initial setup to simulate 100mhz cpu in verilog testbench.