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bart
/
FPGC6
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https://github.com/bartpleiter/FPGC6
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030e6c305e
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EP4CE15
cpu100mhz
fast-cpu-pipeline
main
FPGC6
/
Quartus
/
modules
/
GPU
/
HDMI
bart
e1bb01a621
Cleaned and renamed Quartus project.
1 jaar geleden
..
RGB2HDMI.v
442d51ba85
Added images to documentation, HDMI is working without lvds, init of new sdram controller done.
2 jaren geleden
TMDSenc.v
b74702c915
Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram
2 jaren geleden