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mainpll.vo 18 KB

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  1. //IP Functional Simulation Model
  2. //VERSION_BEGIN 23.1 cbx_mgl 2023:11:29:19:43:53:SC cbx_simgen 2023:11:29:19:33:05:SC VERSION_END
  3. // synthesis VERILOG_INPUT_VERSION VERILOG_2001
  4. // altera message_off 10463
  5. // Copyright (C) 2023 Intel Corporation. All rights reserved.
  6. // Your use of Intel Corporation's design tools, logic functions
  7. // and other software and tools, and any partner logic
  8. // functions, and any output files from any of the foregoing
  9. // (including device programming or simulation files), and any
  10. // associated documentation or information are expressly subject
  11. // to the terms and conditions of the Intel Program License
  12. // Subscription Agreement, the Intel Quartus Prime License Agreement,
  13. // the Intel FPGA IP License Agreement, or other applicable license
  14. // agreement, including, without limitation, that your use is for
  15. // the sole purpose of programming logic devices manufactured by
  16. // Intel and sold by Intel or its authorized distributors. Please
  17. // refer to the applicable agreement for further details, at
  18. // https://fpgasoftware.intel.com/eula.
  19. // You may only use these simulation model output files for simulation
  20. // purposes and expressly not for synthesis or any other purposes (in which
  21. // event Intel disclaims all warranties of any kind).
  22. //synopsys translate_off
  23. //synthesis_resources = altera_pll 1
  24. `timescale 1 ps / 1 ps
  25. module mainpll
  26. (
  27. locked,
  28. outclk_0,
  29. outclk_1,
  30. outclk_2,
  31. outclk_3,
  32. outclk_4,
  33. refclk,
  34. rst) /* synthesis synthesis_clearbox=1 */;
  35. output locked;
  36. output outclk_0;
  37. output outclk_1;
  38. output outclk_2;
  39. output outclk_3;
  40. output outclk_4;
  41. input refclk;
  42. input rst;
  43. wire wire_mainpll_altera_pll_altera_pll_i_2475_locked;
  44. wire [4:0] wire_mainpll_altera_pll_altera_pll_i_2475_outclk;
  45. altera_pll mainpll_altera_pll_altera_pll_i_2475
  46. (
  47. .fbclk(1'b0),
  48. .locked(wire_mainpll_altera_pll_altera_pll_i_2475_locked),
  49. .outclk(wire_mainpll_altera_pll_altera_pll_i_2475_outclk),
  50. .refclk(refclk),
  51. .rst(rst));
  52. defparam
  53. mainpll_altera_pll_altera_pll_i_2475.c_cnt_bypass_en0 = "false",
  54. mainpll_altera_pll_altera_pll_i_2475.c_cnt_bypass_en1 = "false",
  55. mainpll_altera_pll_altera_pll_i_2475.c_cnt_bypass_en10 = "false",
  56. mainpll_altera_pll_altera_pll_i_2475.c_cnt_bypass_en11 = "false",
  57. mainpll_altera_pll_altera_pll_i_2475.c_cnt_bypass_en12 = "false",
  58. mainpll_altera_pll_altera_pll_i_2475.c_cnt_bypass_en13 = "false",
  59. mainpll_altera_pll_altera_pll_i_2475.c_cnt_bypass_en14 = "false",
  60. mainpll_altera_pll_altera_pll_i_2475.c_cnt_bypass_en15 = "false",
  61. mainpll_altera_pll_altera_pll_i_2475.c_cnt_bypass_en16 = "false",
  62. mainpll_altera_pll_altera_pll_i_2475.c_cnt_bypass_en17 = "false",
  63. mainpll_altera_pll_altera_pll_i_2475.c_cnt_bypass_en2 = "false",
  64. mainpll_altera_pll_altera_pll_i_2475.c_cnt_bypass_en3 = "false",
  65. mainpll_altera_pll_altera_pll_i_2475.c_cnt_bypass_en4 = "false",
  66. mainpll_altera_pll_altera_pll_i_2475.c_cnt_bypass_en5 = "false",
  67. mainpll_altera_pll_altera_pll_i_2475.c_cnt_bypass_en6 = "false",
  68. mainpll_altera_pll_altera_pll_i_2475.c_cnt_bypass_en7 = "false",
  69. mainpll_altera_pll_altera_pll_i_2475.c_cnt_bypass_en8 = "false",
  70. mainpll_altera_pll_altera_pll_i_2475.c_cnt_bypass_en9 = "false",
  71. mainpll_altera_pll_altera_pll_i_2475.c_cnt_hi_div0 = 1,
  72. mainpll_altera_pll_altera_pll_i_2475.c_cnt_hi_div1 = 1,
  73. mainpll_altera_pll_altera_pll_i_2475.c_cnt_hi_div10 = 1,
  74. mainpll_altera_pll_altera_pll_i_2475.c_cnt_hi_div11 = 1,
  75. mainpll_altera_pll_altera_pll_i_2475.c_cnt_hi_div12 = 1,
  76. mainpll_altera_pll_altera_pll_i_2475.c_cnt_hi_div13 = 1,
  77. mainpll_altera_pll_altera_pll_i_2475.c_cnt_hi_div14 = 1,
  78. mainpll_altera_pll_altera_pll_i_2475.c_cnt_hi_div15 = 1,
  79. mainpll_altera_pll_altera_pll_i_2475.c_cnt_hi_div16 = 1,
  80. mainpll_altera_pll_altera_pll_i_2475.c_cnt_hi_div17 = 1,
  81. mainpll_altera_pll_altera_pll_i_2475.c_cnt_hi_div2 = 1,
  82. mainpll_altera_pll_altera_pll_i_2475.c_cnt_hi_div3 = 1,
  83. mainpll_altera_pll_altera_pll_i_2475.c_cnt_hi_div4 = 1,
  84. mainpll_altera_pll_altera_pll_i_2475.c_cnt_hi_div5 = 1,
  85. mainpll_altera_pll_altera_pll_i_2475.c_cnt_hi_div6 = 1,
  86. mainpll_altera_pll_altera_pll_i_2475.c_cnt_hi_div7 = 1,
  87. mainpll_altera_pll_altera_pll_i_2475.c_cnt_hi_div8 = 1,
  88. mainpll_altera_pll_altera_pll_i_2475.c_cnt_hi_div9 = 1,
  89. mainpll_altera_pll_altera_pll_i_2475.c_cnt_in_src0 = "ph_mux_clk",
  90. mainpll_altera_pll_altera_pll_i_2475.c_cnt_in_src1 = "ph_mux_clk",
  91. mainpll_altera_pll_altera_pll_i_2475.c_cnt_in_src10 = "ph_mux_clk",
  92. mainpll_altera_pll_altera_pll_i_2475.c_cnt_in_src11 = "ph_mux_clk",
  93. mainpll_altera_pll_altera_pll_i_2475.c_cnt_in_src12 = "ph_mux_clk",
  94. mainpll_altera_pll_altera_pll_i_2475.c_cnt_in_src13 = "ph_mux_clk",
  95. mainpll_altera_pll_altera_pll_i_2475.c_cnt_in_src14 = "ph_mux_clk",
  96. mainpll_altera_pll_altera_pll_i_2475.c_cnt_in_src15 = "ph_mux_clk",
  97. mainpll_altera_pll_altera_pll_i_2475.c_cnt_in_src16 = "ph_mux_clk",
  98. mainpll_altera_pll_altera_pll_i_2475.c_cnt_in_src17 = "ph_mux_clk",
  99. mainpll_altera_pll_altera_pll_i_2475.c_cnt_in_src2 = "ph_mux_clk",
  100. mainpll_altera_pll_altera_pll_i_2475.c_cnt_in_src3 = "ph_mux_clk",
  101. mainpll_altera_pll_altera_pll_i_2475.c_cnt_in_src4 = "ph_mux_clk",
  102. mainpll_altera_pll_altera_pll_i_2475.c_cnt_in_src5 = "ph_mux_clk",
  103. mainpll_altera_pll_altera_pll_i_2475.c_cnt_in_src6 = "ph_mux_clk",
  104. mainpll_altera_pll_altera_pll_i_2475.c_cnt_in_src7 = "ph_mux_clk",
  105. mainpll_altera_pll_altera_pll_i_2475.c_cnt_in_src8 = "ph_mux_clk",
  106. mainpll_altera_pll_altera_pll_i_2475.c_cnt_in_src9 = "ph_mux_clk",
  107. mainpll_altera_pll_altera_pll_i_2475.c_cnt_lo_div0 = 1,
  108. mainpll_altera_pll_altera_pll_i_2475.c_cnt_lo_div1 = 1,
  109. mainpll_altera_pll_altera_pll_i_2475.c_cnt_lo_div10 = 1,
  110. mainpll_altera_pll_altera_pll_i_2475.c_cnt_lo_div11 = 1,
  111. mainpll_altera_pll_altera_pll_i_2475.c_cnt_lo_div12 = 1,
  112. mainpll_altera_pll_altera_pll_i_2475.c_cnt_lo_div13 = 1,
  113. mainpll_altera_pll_altera_pll_i_2475.c_cnt_lo_div14 = 1,
  114. mainpll_altera_pll_altera_pll_i_2475.c_cnt_lo_div15 = 1,
  115. mainpll_altera_pll_altera_pll_i_2475.c_cnt_lo_div16 = 1,
  116. mainpll_altera_pll_altera_pll_i_2475.c_cnt_lo_div17 = 1,
  117. mainpll_altera_pll_altera_pll_i_2475.c_cnt_lo_div2 = 1,
  118. mainpll_altera_pll_altera_pll_i_2475.c_cnt_lo_div3 = 1,
  119. mainpll_altera_pll_altera_pll_i_2475.c_cnt_lo_div4 = 1,
  120. mainpll_altera_pll_altera_pll_i_2475.c_cnt_lo_div5 = 1,
  121. mainpll_altera_pll_altera_pll_i_2475.c_cnt_lo_div6 = 1,
  122. mainpll_altera_pll_altera_pll_i_2475.c_cnt_lo_div7 = 1,
  123. mainpll_altera_pll_altera_pll_i_2475.c_cnt_lo_div8 = 1,
  124. mainpll_altera_pll_altera_pll_i_2475.c_cnt_lo_div9 = 1,
  125. mainpll_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en0 = "false",
  126. mainpll_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en1 = "false",
  127. mainpll_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en10 = "false",
  128. mainpll_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en11 = "false",
  129. mainpll_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en12 = "false",
  130. mainpll_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en13 = "false",
  131. mainpll_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en14 = "false",
  132. mainpll_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en15 = "false",
  133. mainpll_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en16 = "false",
  134. mainpll_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en17 = "false",
  135. mainpll_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en2 = "false",
  136. mainpll_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en3 = "false",
  137. mainpll_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en4 = "false",
  138. mainpll_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en5 = "false",
  139. mainpll_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en6 = "false",
  140. mainpll_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en7 = "false",
  141. mainpll_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en8 = "false",
  142. mainpll_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en9 = "false",
  143. mainpll_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst0 = 0,
  144. mainpll_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst1 = 0,
  145. mainpll_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst10 = 0,
  146. mainpll_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst11 = 0,
  147. mainpll_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst12 = 0,
  148. mainpll_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst13 = 0,
  149. mainpll_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst14 = 0,
  150. mainpll_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst15 = 0,
  151. mainpll_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst16 = 0,
  152. mainpll_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst17 = 0,
  153. mainpll_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst2 = 0,
  154. mainpll_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst3 = 0,
  155. mainpll_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst4 = 0,
  156. mainpll_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst5 = 0,
  157. mainpll_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst6 = 0,
  158. mainpll_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst7 = 0,
  159. mainpll_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst8 = 0,
  160. mainpll_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst9 = 0,
  161. mainpll_altera_pll_altera_pll_i_2475.c_cnt_prst0 = 1,
  162. mainpll_altera_pll_altera_pll_i_2475.c_cnt_prst1 = 1,
  163. mainpll_altera_pll_altera_pll_i_2475.c_cnt_prst10 = 1,
  164. mainpll_altera_pll_altera_pll_i_2475.c_cnt_prst11 = 1,
  165. mainpll_altera_pll_altera_pll_i_2475.c_cnt_prst12 = 1,
  166. mainpll_altera_pll_altera_pll_i_2475.c_cnt_prst13 = 1,
  167. mainpll_altera_pll_altera_pll_i_2475.c_cnt_prst14 = 1,
  168. mainpll_altera_pll_altera_pll_i_2475.c_cnt_prst15 = 1,
  169. mainpll_altera_pll_altera_pll_i_2475.c_cnt_prst16 = 1,
  170. mainpll_altera_pll_altera_pll_i_2475.c_cnt_prst17 = 1,
  171. mainpll_altera_pll_altera_pll_i_2475.c_cnt_prst2 = 1,
  172. mainpll_altera_pll_altera_pll_i_2475.c_cnt_prst3 = 1,
  173. mainpll_altera_pll_altera_pll_i_2475.c_cnt_prst4 = 1,
  174. mainpll_altera_pll_altera_pll_i_2475.c_cnt_prst5 = 1,
  175. mainpll_altera_pll_altera_pll_i_2475.c_cnt_prst6 = 1,
  176. mainpll_altera_pll_altera_pll_i_2475.c_cnt_prst7 = 1,
  177. mainpll_altera_pll_altera_pll_i_2475.c_cnt_prst8 = 1,
  178. mainpll_altera_pll_altera_pll_i_2475.c_cnt_prst9 = 1,
  179. mainpll_altera_pll_altera_pll_i_2475.clock_name_0 = "UNUSED",
  180. mainpll_altera_pll_altera_pll_i_2475.clock_name_1 = "UNUSED",
  181. mainpll_altera_pll_altera_pll_i_2475.clock_name_2 = "UNUSED",
  182. mainpll_altera_pll_altera_pll_i_2475.clock_name_3 = "UNUSED",
  183. mainpll_altera_pll_altera_pll_i_2475.clock_name_4 = "UNUSED",
  184. mainpll_altera_pll_altera_pll_i_2475.clock_name_5 = "UNUSED",
  185. mainpll_altera_pll_altera_pll_i_2475.clock_name_6 = "UNUSED",
  186. mainpll_altera_pll_altera_pll_i_2475.clock_name_7 = "UNUSED",
  187. mainpll_altera_pll_altera_pll_i_2475.clock_name_8 = "UNUSED",
  188. mainpll_altera_pll_altera_pll_i_2475.clock_name_global_0 = "false",
  189. mainpll_altera_pll_altera_pll_i_2475.clock_name_global_1 = "false",
  190. mainpll_altera_pll_altera_pll_i_2475.clock_name_global_2 = "false",
  191. mainpll_altera_pll_altera_pll_i_2475.clock_name_global_3 = "false",
  192. mainpll_altera_pll_altera_pll_i_2475.clock_name_global_4 = "false",
  193. mainpll_altera_pll_altera_pll_i_2475.clock_name_global_5 = "false",
  194. mainpll_altera_pll_altera_pll_i_2475.clock_name_global_6 = "false",
  195. mainpll_altera_pll_altera_pll_i_2475.clock_name_global_7 = "false",
  196. mainpll_altera_pll_altera_pll_i_2475.clock_name_global_8 = "false",
  197. mainpll_altera_pll_altera_pll_i_2475.data_rate = 0,
  198. mainpll_altera_pll_altera_pll_i_2475.deserialization_factor = 4,
  199. mainpll_altera_pll_altera_pll_i_2475.duty_cycle0 = 50,
  200. mainpll_altera_pll_altera_pll_i_2475.duty_cycle1 = 50,
  201. mainpll_altera_pll_altera_pll_i_2475.duty_cycle10 = 50,
  202. mainpll_altera_pll_altera_pll_i_2475.duty_cycle11 = 50,
  203. mainpll_altera_pll_altera_pll_i_2475.duty_cycle12 = 50,
  204. mainpll_altera_pll_altera_pll_i_2475.duty_cycle13 = 50,
  205. mainpll_altera_pll_altera_pll_i_2475.duty_cycle14 = 50,
  206. mainpll_altera_pll_altera_pll_i_2475.duty_cycle15 = 50,
  207. mainpll_altera_pll_altera_pll_i_2475.duty_cycle16 = 50,
  208. mainpll_altera_pll_altera_pll_i_2475.duty_cycle17 = 50,
  209. mainpll_altera_pll_altera_pll_i_2475.duty_cycle2 = 50,
  210. mainpll_altera_pll_altera_pll_i_2475.duty_cycle3 = 50,
  211. mainpll_altera_pll_altera_pll_i_2475.duty_cycle4 = 50,
  212. mainpll_altera_pll_altera_pll_i_2475.duty_cycle5 = 50,
  213. mainpll_altera_pll_altera_pll_i_2475.duty_cycle6 = 50,
  214. mainpll_altera_pll_altera_pll_i_2475.duty_cycle7 = 50,
  215. mainpll_altera_pll_altera_pll_i_2475.duty_cycle8 = 50,
  216. mainpll_altera_pll_altera_pll_i_2475.duty_cycle9 = 50,
  217. mainpll_altera_pll_altera_pll_i_2475.fractional_vco_multiplier = "false",
  218. mainpll_altera_pll_altera_pll_i_2475.m_cnt_bypass_en = "false",
  219. mainpll_altera_pll_altera_pll_i_2475.m_cnt_hi_div = 1,
  220. mainpll_altera_pll_altera_pll_i_2475.m_cnt_lo_div = 1,
  221. mainpll_altera_pll_altera_pll_i_2475.m_cnt_odd_div_duty_en = "false",
  222. mainpll_altera_pll_altera_pll_i_2475.mimic_fbclk_type = "gclk",
  223. mainpll_altera_pll_altera_pll_i_2475.n_cnt_bypass_en = "false",
  224. mainpll_altera_pll_altera_pll_i_2475.n_cnt_hi_div = 1,
  225. mainpll_altera_pll_altera_pll_i_2475.n_cnt_lo_div = 1,
  226. mainpll_altera_pll_altera_pll_i_2475.n_cnt_odd_div_duty_en = "false",
  227. mainpll_altera_pll_altera_pll_i_2475.number_of_clocks = 5,
  228. mainpll_altera_pll_altera_pll_i_2475.operation_mode = "direct",
  229. mainpll_altera_pll_altera_pll_i_2475.output_clock_frequency0 = "100.000000 MHz",
  230. mainpll_altera_pll_altera_pll_i_2475.output_clock_frequency1 = "100.000000 MHz",
  231. mainpll_altera_pll_altera_pll_i_2475.output_clock_frequency10 = "0 MHz",
  232. mainpll_altera_pll_altera_pll_i_2475.output_clock_frequency11 = "0 MHz",
  233. mainpll_altera_pll_altera_pll_i_2475.output_clock_frequency12 = "0 MHz",
  234. mainpll_altera_pll_altera_pll_i_2475.output_clock_frequency13 = "0 MHz",
  235. mainpll_altera_pll_altera_pll_i_2475.output_clock_frequency14 = "0 MHz",
  236. mainpll_altera_pll_altera_pll_i_2475.output_clock_frequency15 = "0 MHz",
  237. mainpll_altera_pll_altera_pll_i_2475.output_clock_frequency16 = "0 MHz",
  238. mainpll_altera_pll_altera_pll_i_2475.output_clock_frequency17 = "0 MHz",
  239. mainpll_altera_pll_altera_pll_i_2475.output_clock_frequency2 = "50.000000 MHz",
  240. mainpll_altera_pll_altera_pll_i_2475.output_clock_frequency3 = "25.000000 MHz",
  241. mainpll_altera_pll_altera_pll_i_2475.output_clock_frequency4 = "125.000000 MHz",
  242. mainpll_altera_pll_altera_pll_i_2475.output_clock_frequency5 = "0 MHz",
  243. mainpll_altera_pll_altera_pll_i_2475.output_clock_frequency6 = "0 MHz",
  244. mainpll_altera_pll_altera_pll_i_2475.output_clock_frequency7 = "0 MHz",
  245. mainpll_altera_pll_altera_pll_i_2475.output_clock_frequency8 = "0 MHz",
  246. mainpll_altera_pll_altera_pll_i_2475.output_clock_frequency9 = "0 MHz",
  247. mainpll_altera_pll_altera_pll_i_2475.phase_shift0 = "0 ps",
  248. mainpll_altera_pll_altera_pll_i_2475.phase_shift1 = "5000 ps",
  249. mainpll_altera_pll_altera_pll_i_2475.phase_shift10 = "0 ps",
  250. mainpll_altera_pll_altera_pll_i_2475.phase_shift11 = "0 ps",
  251. mainpll_altera_pll_altera_pll_i_2475.phase_shift12 = "0 ps",
  252. mainpll_altera_pll_altera_pll_i_2475.phase_shift13 = "0 ps",
  253. mainpll_altera_pll_altera_pll_i_2475.phase_shift14 = "0 ps",
  254. mainpll_altera_pll_altera_pll_i_2475.phase_shift15 = "0 ps",
  255. mainpll_altera_pll_altera_pll_i_2475.phase_shift16 = "0 ps",
  256. mainpll_altera_pll_altera_pll_i_2475.phase_shift17 = "0 ps",
  257. mainpll_altera_pll_altera_pll_i_2475.phase_shift2 = "0 ps",
  258. mainpll_altera_pll_altera_pll_i_2475.phase_shift3 = "0 ps",
  259. mainpll_altera_pll_altera_pll_i_2475.phase_shift4 = "0 ps",
  260. mainpll_altera_pll_altera_pll_i_2475.phase_shift5 = "0 ps",
  261. mainpll_altera_pll_altera_pll_i_2475.phase_shift6 = "0 ps",
  262. mainpll_altera_pll_altera_pll_i_2475.phase_shift7 = "0 ps",
  263. mainpll_altera_pll_altera_pll_i_2475.phase_shift8 = "0 ps",
  264. mainpll_altera_pll_altera_pll_i_2475.phase_shift9 = "0 ps",
  265. mainpll_altera_pll_altera_pll_i_2475.pll_auto_clk_sw_en = "false",
  266. mainpll_altera_pll_altera_pll_i_2475.pll_bw_sel = "low",
  267. mainpll_altera_pll_altera_pll_i_2475.pll_bwctrl = 0,
  268. mainpll_altera_pll_altera_pll_i_2475.pll_clk_loss_sw_en = "false",
  269. mainpll_altera_pll_altera_pll_i_2475.pll_clk_sw_dly = 0,
  270. mainpll_altera_pll_altera_pll_i_2475.pll_clkin_0_src = "clk_0",
  271. mainpll_altera_pll_altera_pll_i_2475.pll_clkin_1_src = "clk_0",
  272. mainpll_altera_pll_altera_pll_i_2475.pll_cp_current = 0,
  273. mainpll_altera_pll_altera_pll_i_2475.pll_dsm_out_sel = "1st_order",
  274. mainpll_altera_pll_altera_pll_i_2475.pll_extclk_0_cnt_src = "pll_extclk_cnt_src_vss",
  275. mainpll_altera_pll_altera_pll_i_2475.pll_extclk_1_cnt_src = "pll_extclk_cnt_src_vss",
  276. mainpll_altera_pll_altera_pll_i_2475.pll_fbclk_mux_1 = "glb",
  277. mainpll_altera_pll_altera_pll_i_2475.pll_fbclk_mux_2 = "fb_1",
  278. mainpll_altera_pll_altera_pll_i_2475.pll_fractional_cout = 24,
  279. mainpll_altera_pll_altera_pll_i_2475.pll_fractional_division = 1,
  280. mainpll_altera_pll_altera_pll_i_2475.pll_m_cnt_in_src = "ph_mux_clk",
  281. mainpll_altera_pll_altera_pll_i_2475.pll_manu_clk_sw_en = "false",
  282. mainpll_altera_pll_altera_pll_i_2475.pll_output_clk_frequency = "0 MHz",
  283. mainpll_altera_pll_altera_pll_i_2475.pll_slf_rst = "false",
  284. mainpll_altera_pll_altera_pll_i_2475.pll_subtype = "General",
  285. mainpll_altera_pll_altera_pll_i_2475.pll_type = "General",
  286. mainpll_altera_pll_altera_pll_i_2475.pll_vco_div = 1,
  287. mainpll_altera_pll_altera_pll_i_2475.pll_vcoph_div = 1,
  288. mainpll_altera_pll_altera_pll_i_2475.refclk1_frequency = "0 MHz",
  289. mainpll_altera_pll_altera_pll_i_2475.reference_clock_frequency = "50.0 MHz",
  290. mainpll_altera_pll_altera_pll_i_2475.sim_additional_refclk_cycles_to_lock = 0;
  291. assign
  292. locked = wire_mainpll_altera_pll_altera_pll_i_2475_locked,
  293. outclk_0 = wire_mainpll_altera_pll_altera_pll_i_2475_outclk[0],
  294. outclk_1 = wire_mainpll_altera_pll_altera_pll_i_2475_outclk[1],
  295. outclk_2 = wire_mainpll_altera_pll_altera_pll_i_2475_outclk[2],
  296. outclk_3 = wire_mainpll_altera_pll_altera_pll_i_2475_outclk[3],
  297. outclk_4 = wire_mainpll_altera_pll_altera_pll_i_2475_outclk[4];
  298. endmodule //mainpll
  299. //synopsys translate_on
  300. //VALID FILE