ddr_bb.v 3.3 KB

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  1. // megafunction wizard: %ALTDDIO_OUT%VBB%
  2. // GENERATION: STANDARD
  3. // VERSION: WM1.0
  4. // MODULE: ALTDDIO_OUT
  5. // ============================================================
  6. // File Name: ddr.v
  7. // Megafunction Name(s):
  8. // ALTDDIO_OUT
  9. //
  10. // Simulation Library Files(s):
  11. //
  12. // ============================================================
  13. // ************************************************************
  14. // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
  15. //
  16. // 23.1std.0 Build 991 11/28/2023 SC Lite Edition
  17. // ************************************************************
  18. //Copyright (C) 2023 Intel Corporation. All rights reserved.
  19. //Your use of Intel Corporation's design tools, logic functions
  20. //and other software and tools, and any partner logic
  21. //functions, and any output files from any of the foregoing
  22. //(including device programming or simulation files), and any
  23. //associated documentation or information are expressly subject
  24. //to the terms and conditions of the Intel Program License
  25. //Subscription Agreement, the Intel Quartus Prime License Agreement,
  26. //the Intel FPGA IP License Agreement, or other applicable license
  27. //agreement, including, without limitation, that your use is for
  28. //the sole purpose of programming logic devices manufactured by
  29. //Intel and sold by Intel or its authorized distributors. Please
  30. //refer to the applicable agreement for further details, at
  31. //https://fpgasoftware.intel.com/eula.
  32. module ddr (
  33. datain_h,
  34. datain_l,
  35. outclock,
  36. dataout);
  37. input [0:0] datain_h;
  38. input [0:0] datain_l;
  39. input outclock;
  40. output [0:0] dataout;
  41. endmodule
  42. // ============================================================
  43. // CNX file retrieval info
  44. // ============================================================
  45. // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
  46. // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
  47. // Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF"
  48. // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
  49. // Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
  50. // Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
  51. // Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
  52. // Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED"
  53. // Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
  54. // Retrieval info: CONSTANT: WIDTH NUMERIC "1"
  55. // Retrieval info: USED_PORT: datain_h 0 0 1 0 INPUT NODEFVAL "datain_h[0..0]"
  56. // Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 1 0
  57. // Retrieval info: USED_PORT: datain_l 0 0 1 0 INPUT NODEFVAL "datain_l[0..0]"
  58. // Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 1 0
  59. // Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]"
  60. // Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0
  61. // Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock"
  62. // Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
  63. // Retrieval info: GEN_FILE: TYPE_NORMAL ddr.v TRUE FALSE
  64. // Retrieval info: GEN_FILE: TYPE_NORMAL ddr.qip TRUE FALSE
  65. // Retrieval info: GEN_FILE: TYPE_NORMAL ddr.bsf FALSE TRUE
  66. // Retrieval info: GEN_FILE: TYPE_NORMAL ddr_inst.v FALSE TRUE
  67. // Retrieval info: GEN_FILE: TYPE_NORMAL ddr_bb.v TRUE TRUE
  68. // Retrieval info: GEN_FILE: TYPE_NORMAL ddr.inc FALSE TRUE
  69. // Retrieval info: GEN_FILE: TYPE_NORMAL ddr.cmp FALSE TRUE
  70. // Retrieval info: GEN_FILE: TYPE_NORMAL ddr.ppf TRUE FALSE