bartpleiter 9438941e15 Initial setup to simulate 100mhz cpu in verilog testbench. 5 meses atrás
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Bootloaders 7e81e7fa17 Added files missing from last commit (L1I cache). 1 ano atrás
SimTests 28bcde6466 New SDRAM controller that uses both SDRAM chips. Now separate bus from MU for better performance, as controller runs at 100MHz. Also updated some debug code as debugging was needed. Tested working in hardware. 2x performance boost in some cases. 1 ano atrás
Assembler.py ddd3d60235 Added Fixed-Point BCC library, including a FPCALC application to test it. MULTFP instruction is added to assembler, and some library functions were added during development. 1 ano atrás
CompileInstruction.py 01a00e1603 Update new repo link, add requirements.txt. 7 meses atrás
buildToVerilog.sh 28bcde6466 New SDRAM controller that uses both SDRAM chips. Now separate bus from MU for better performance, as controller runs at 100MHz. Also updated some debug code as debugging was needed. Tested working in hardware. 2x performance boost in some cases. 1 ano atrás
compileAndSend.sh 1026f4776c Cleaned up some files 2 anos atrás
simulate.sh 9438941e15 Initial setup to simulate 100mhz cpu in verilog testbench. 5 meses atrás