[*]
[*] GTKWave Analyzer v3.3.116 (w)1999-2023 BSI
[*] Sat Sep 21 12:22:32 2024
[*]
[dumpfile] "/home/bart/Documents/FPGA/FPGC6/Verilog/output/wave.vcd"
[dumpfile_mtime] "Sat Aug 31 18:28:43 2024"
[dumpfile_size] 86361
[savefile] "/home/bart/Documents/FPGA/FPGC6/Verilog/output/B32P.gtkw"
[timestart] 0
[size] 1920 1001
[pos] -1 -1
*-7.414134 428 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] FPGC_tb.
[treeopen] FPGC_tb.fpgc.
[treeopen] FPGC_tb.fpgc.cpu.
[treeopen] FPGC_tb.fpgc.memoryunit.
[sst_width] 278
[signals_width] 251
[sst_expanded] 1
[sst_vpaned_height] 264
@28
FPGC_tb.clk
FPGC_tb.fpgc.reset
@200
-
-CPU
@24
FPGC_tb.fpgc.cpu.pc_FE_prev[31:0]
FPGC_tb.fpgc.cpu.pc_FE[31:0]
FPGC_tb.fpgc.cpu.jump_addr_MEM[31:0]
@28
FPGC_tb.fpgc.cpu.instr_DE[31:0]
FPGC_tb.fpgc.cpu.instr_EX[31:0]
FPGC_tb.fpgc.cpu.instr_MEM[31:0]
FPGC_tb.fpgc.cpu.instr_WB[31:0]
@200
-
@28
FPGC_tb.fpgc.cpu.stall_FE
FPGC_tb.fpgc.cpu.stall_DE
FPGC_tb.fpgc.cpu.stall_EX
FPGC_tb.fpgc.cpu.stall_MEM
FPGC_tb.fpgc.cpu.stall_WB
@200
-
@29
FPGC_tb.fpgc.cpu.flush_DE
@28
FPGC_tb.fpgc.cpu.flush_EX
FPGC_tb.fpgc.cpu.flush_FE
@200
-
@28
FPGC_tb.fpgc.cpu.datamem_busy_MEM
@200
-
-Registers
@24
FPGC_tb.fpgc.cpu.regbank.addr_d[3:0]
FPGC_tb.fpgc.cpu.regbank.data_d[31:0]
FPGC_tb.fpgc.cpu.regbank.we
@200
-
@24
FPGC_tb.fpgc.cpu.regbank.addr_a[3:0]
FPGC_tb.fpgc.cpu.regbank.data_a[31:0]
FPGC_tb.fpgc.cpu.regbank.addr_b[3:0]
FPGC_tb.fpgc.cpu.regbank.data_b[31:0]
@200
-
-SRAM
@28
FPGC_tb.fpgc.memoryunit.sram.cpu_clk
@24
FPGC_tb.fpgc.memoryunit.sram.cpu_addr[11:0]
@28
FPGC_tb.fpgc.memoryunit.sram.cpu_we
@24
FPGC_tb.fpgc.memoryunit.sram.cpu_d[31:0]
@28
FPGC_tb.fpgc.memoryunit.sram.cpu_q[31:0]
@200
-
-MU
@24
FPGC_tb.fpgc.memoryunit.clk
FPGC_tb.fpgc.memoryunit.bus_addr[26:0]
FPGC_tb.fpgc.memoryunit.bus_we
FPGC_tb.fpgc.memoryunit.bus_data[31:0]
FPGC_tb.fpgc.memoryunit.bus_start
FPGC_tb.fpgc.memoryunit.bus_done_next
@28
FPGC_tb.fpgc.memoryunit.bus_start
FPGC_tb.fpgc.memoryunit.bus_ready_reg
@24
FPGC_tb.fpgc.memoryunit.bus_done
@200
-
-Instr Mem
@28
FPGC_tb.fpgc.cpu.instrMem.hold
FPGC_tb.fpgc.cpu.instrMem.hold_reg
FPGC_tb.fpgc.cpu.instrMem.clear
@24
FPGC_tb.fpgc.cpu.instrMem.ignoreNext
FPGC_tb.fpgc.cpu.instrMem.bus_start
@28
FPGC_tb.fpgc.cpu.instrMem.bus_start_prev
FPGC_tb.fpgc.cpu.instrMem.bus_ready
@24
FPGC_tb.fpgc.cpu.instrMem.bus_done
FPGC_tb.fpgc.cpu.instrMem.hit
@28
FPGC_tb.fpgc.cpu.instrMem.hit_prev
@24
FPGC_tb.fpgc.cpu.instrMem.addr[31:0]
@28
FPGC_tb.fpgc.cpu.instrMem.bus_q[31:0]
FPGC_tb.fpgc.cpu.instrMem.q[31:0]
@200
-
@24
FPGC_tb.fpgc.cpu.forward_a[1:0]
FPGC_tb.fpgc.cpu.forward_b[1:0]
@200
-
-Data Mem
@28
FPGC_tb.fpgc.cpu.dataMem.hold
FPGC_tb.fpgc.cpu.dataMem.clear
@24
FPGC_tb.fpgc.cpu.dataMem.data[31:0]
FPGC_tb.fpgc.cpu.dataMem.we
FPGC_tb.fpgc.cpu.dataMem.re
@28
FPGC_tb.fpgc.cpu.dataMem.read_or_write_edge
@24
FPGC_tb.fpgc.cpu.dataMem.busy
@200
-
@24
FPGC_tb.fpgc.cpu.dataMem.bus_start
FPGC_tb.fpgc.cpu.dataMem.bus_we
FPGC_tb.fpgc.cpu.dataMem.bus_addr[31:0]
FPGC_tb.fpgc.cpu.dataMem.bus_data[31:0]
FPGC_tb.fpgc.cpu.dataMem.bus_done
FPGC_tb.fpgc.cpu.dataMem.q[31:0]
@200
-
-Arbiter
@24
FPGC_tb.fpgc.cpu.arbiter.start_a
FPGC_tb.fpgc.cpu.arbiter.done_a
FPGC_tb.fpgc.cpu.arbiter.addr_a[31:0]
FPGC_tb.fpgc.cpu.arbiter.data_a[31:0]
@28
FPGC_tb.fpgc.cpu.arbiter.ready_a
@200
-
@24
FPGC_tb.fpgc.cpu.arbiter.start_b
FPGC_tb.fpgc.cpu.arbiter.we_b
FPGC_tb.fpgc.cpu.arbiter.addr_b[31:0]
FPGC_tb.fpgc.cpu.arbiter.data_b[31:0]
FPGC_tb.fpgc.cpu.arbiter.port_b_access
@28
FPGC_tb.fpgc.cpu.arbiter.ready_b
@200
-
@24
FPGC_tb.fpgc.cpu.arbiter.state[2:0]
@200
-
@24
FPGC_tb.fpgc.cpu.arbiter.bus_start
FPGC_tb.fpgc.cpu.arbiter.bus_we
FPGC_tb.fpgc.cpu.arbiter.bus_addr[26:0]
FPGC_tb.fpgc.cpu.arbiter.bus_data[31:0]
FPGC_tb.fpgc.cpu.arbiter.bus_done
@28
FPGC_tb.fpgc.cpu.arbiter.bus_ready
@200
-
-Stack
@24
FPGC_tb.fpgc.cpu.stack.useRamResult
FPGC_tb.fpgc.cpu.stack.ramResult[31:0]
FPGC_tb.fpgc.cpu.stack.push
FPGC_tb.fpgc.cpu.stack.pop
FPGC_tb.fpgc.cpu.stack.d[31:0]
FPGC_tb.fpgc.cpu.stack.q[31:0]
[pattern_trace] 1
[pattern_trace] 0