//IP Functional Simulation Model //VERSION_BEGIN 21.1 cbx_mgl 2022:06:23:22:26:17:SJ cbx_simgen 2022:06:23:22:02:32:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 // Copyright (C) 2022 Intel Corporation. All rights reserved. // Your use of Intel Corporation's design tools, logic functions // and other software and tools, and any partner logic // functions, and any output files from any of the foregoing // (including device programming or simulation files), and any // associated documentation or information are expressly subject // to the terms and conditions of the Intel Program License // Subscription Agreement, the Intel Quartus Prime License Agreement, // the Intel FPGA IP License Agreement, or other applicable license // agreement, including, without limitation, that your use is for // the sole purpose of programming logic devices manufactured by // Intel and sold by Intel or its authorized distributors. Please // refer to the applicable agreement for further details, at // https://fpgasoftware.intel.com/eula. // You may only use these simulation model output files for simulation // purposes and expressly not for synthesis or any other purposes (in which // event Intel disclaims all warranties of any kind). //synopsys translate_off //synthesis_resources = altera_pll 1 `timescale 1 ps / 1 ps module clock_pll_v ( locked, outclk_0, outclk_1, outclk_2, outclk_3, outclk_4, refclk, rst) /* synthesis synthesis_clearbox=1 */; output locked; output outclk_0; output outclk_1; output outclk_2; output outclk_3; output outclk_4; input refclk; input rst; wire wire_clock_pll_v_altera_pll_altera_pll_i_2475_locked; wire [4:0] wire_clock_pll_v_altera_pll_altera_pll_i_2475_outclk; altera_pll clock_pll_v_altera_pll_altera_pll_i_2475 ( .fbclk(1'b0), .locked(wire_clock_pll_v_altera_pll_altera_pll_i_2475_locked), .outclk(wire_clock_pll_v_altera_pll_altera_pll_i_2475_outclk), .refclk(refclk), .rst(rst)); defparam clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en0 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en1 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en10 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en11 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en12 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en13 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en14 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en15 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en16 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en17 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en2 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en3 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en4 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en5 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en6 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en7 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en8 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_bypass_en9 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div0 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div1 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div10 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div11 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div12 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div13 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div14 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div15 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div16 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div17 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div2 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div3 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div4 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div5 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div6 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div7 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div8 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_hi_div9 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src0 = "ph_mux_clk", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src1 = "ph_mux_clk", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src10 = "ph_mux_clk", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src11 = "ph_mux_clk", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src12 = "ph_mux_clk", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src13 = "ph_mux_clk", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src14 = "ph_mux_clk", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src15 = "ph_mux_clk", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src16 = "ph_mux_clk", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src17 = "ph_mux_clk", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src2 = "ph_mux_clk", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src3 = "ph_mux_clk", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src4 = "ph_mux_clk", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src5 = "ph_mux_clk", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src6 = "ph_mux_clk", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src7 = "ph_mux_clk", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src8 = "ph_mux_clk", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_in_src9 = "ph_mux_clk", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div0 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div1 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div10 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div11 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div12 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div13 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div14 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div15 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div16 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div17 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div2 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div3 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div4 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div5 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div6 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div7 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div8 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_lo_div9 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en0 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en1 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en10 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en11 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en12 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en13 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en14 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en15 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en16 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en17 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en2 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en3 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en4 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en5 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en6 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en7 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en8 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_odd_div_duty_en9 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst0 = 0, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst1 = 0, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst10 = 0, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst11 = 0, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst12 = 0, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst13 = 0, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst14 = 0, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst15 = 0, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst16 = 0, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst17 = 0, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst2 = 0, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst3 = 0, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst4 = 0, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst5 = 0, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst6 = 0, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst7 = 0, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst8 = 0, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_ph_mux_prst9 = 0, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst0 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst1 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst10 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst11 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst12 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst13 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst14 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst15 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst16 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst17 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst2 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst3 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst4 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst5 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst6 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst7 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst8 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.c_cnt_prst9 = 1, clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_0 = "UNUSED", clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_1 = "UNUSED", clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_2 = "UNUSED", clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_3 = "UNUSED", clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_4 = "UNUSED", clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_5 = "UNUSED", clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_6 = "UNUSED", clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_7 = "UNUSED", clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_8 = "UNUSED", clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_global_0 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_global_1 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_global_2 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_global_3 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_global_4 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_global_5 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_global_6 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_global_7 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.clock_name_global_8 = "false", clock_pll_v_altera_pll_altera_pll_i_2475.data_rate = 0, clock_pll_v_altera_pll_altera_pll_i_2475.deserialization_factor = 4, clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle0 = 50, clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle1 = 50, clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle10 = 50, clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle11 = 50, clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle12 = 50, clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle13 = 50, clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle14 = 50, clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle15 = 50, clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle16 = 50, clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle17 = 50, clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle2 = 50, clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle3 = 50, clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle4 = 50, clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle5 = 50, clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle6 = 50, clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle7 = 50, clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle8 = 50, clock_pll_v_altera_pll_altera_pll_i_2475.duty_cycle9 = 50, clock_pll_v_altera_pll_altera_pll_i_2475.fractional_vco_multiplier = "false", clock_pll_v_altera_pll_altera_pll_i_2475.m_cnt_bypass_en = "false", clock_pll_v_altera_pll_altera_pll_i_2475.m_cnt_hi_div = 1, clock_pll_v_altera_pll_altera_pll_i_2475.m_cnt_lo_div = 1, clock_pll_v_altera_pll_altera_pll_i_2475.m_cnt_odd_div_duty_en = "false", clock_pll_v_altera_pll_altera_pll_i_2475.mimic_fbclk_type = "gclk", clock_pll_v_altera_pll_altera_pll_i_2475.n_cnt_bypass_en = "false", clock_pll_v_altera_pll_altera_pll_i_2475.n_cnt_hi_div = 1, clock_pll_v_altera_pll_altera_pll_i_2475.n_cnt_lo_div = 1, clock_pll_v_altera_pll_altera_pll_i_2475.n_cnt_odd_div_duty_en = "false", clock_pll_v_altera_pll_altera_pll_i_2475.number_of_clocks = 5, clock_pll_v_altera_pll_altera_pll_i_2475.operation_mode = "direct", clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency0 = "25.000000 MHz", clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency1 = "125.000000 MHz", clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency10 = "0 MHz", clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency11 = "0 MHz", clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency12 = "0 MHz", clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency13 = "0 MHz", clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency14 = "0 MHz", clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency15 = "0 MHz", clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency16 = "0 MHz", clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency17 = "0 MHz", clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency2 = "100.000000 MHz", clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency3 = "100.000000 MHz", clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency4 = "50.000000 MHz", clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency5 = "0 MHz", clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency6 = "0 MHz", clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency7 = "0 MHz", clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency8 = "0 MHz", clock_pll_v_altera_pll_altera_pll_i_2475.output_clock_frequency9 = "0 MHz", clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift0 = "0 ps", clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift1 = "0 ps", clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift10 = "0 ps", clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift11 = "0 ps", clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift12 = "0 ps", clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift13 = "0 ps", clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift14 = "0 ps", clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift15 = "0 ps", clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift16 = "0 ps", clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift17 = "0 ps", clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift2 = "0 ps", clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift3 = "2500 ps", clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift4 = "0 ps", clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift5 = "0 ps", clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift6 = "0 ps", clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift7 = "0 ps", clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift8 = "0 ps", clock_pll_v_altera_pll_altera_pll_i_2475.phase_shift9 = "0 ps", clock_pll_v_altera_pll_altera_pll_i_2475.pll_auto_clk_sw_en = "false", clock_pll_v_altera_pll_altera_pll_i_2475.pll_bw_sel = "low", clock_pll_v_altera_pll_altera_pll_i_2475.pll_bwctrl = 0, clock_pll_v_altera_pll_altera_pll_i_2475.pll_clk_loss_sw_en = "false", clock_pll_v_altera_pll_altera_pll_i_2475.pll_clk_sw_dly = 0, clock_pll_v_altera_pll_altera_pll_i_2475.pll_clkin_0_src = "clk_0", clock_pll_v_altera_pll_altera_pll_i_2475.pll_clkin_1_src = "clk_0", clock_pll_v_altera_pll_altera_pll_i_2475.pll_cp_current = 0, clock_pll_v_altera_pll_altera_pll_i_2475.pll_dsm_out_sel = "1st_order", clock_pll_v_altera_pll_altera_pll_i_2475.pll_extclk_0_cnt_src = "pll_extclk_cnt_src_vss", clock_pll_v_altera_pll_altera_pll_i_2475.pll_extclk_1_cnt_src = "pll_extclk_cnt_src_vss", clock_pll_v_altera_pll_altera_pll_i_2475.pll_fbclk_mux_1 = "glb", clock_pll_v_altera_pll_altera_pll_i_2475.pll_fbclk_mux_2 = "fb_1", clock_pll_v_altera_pll_altera_pll_i_2475.pll_fractional_cout = 24, clock_pll_v_altera_pll_altera_pll_i_2475.pll_fractional_division = 1, clock_pll_v_altera_pll_altera_pll_i_2475.pll_m_cnt_in_src = "ph_mux_clk", clock_pll_v_altera_pll_altera_pll_i_2475.pll_manu_clk_sw_en = "false", clock_pll_v_altera_pll_altera_pll_i_2475.pll_output_clk_frequency = "0 MHz", clock_pll_v_altera_pll_altera_pll_i_2475.pll_slf_rst = "false", clock_pll_v_altera_pll_altera_pll_i_2475.pll_subtype = "General", clock_pll_v_altera_pll_altera_pll_i_2475.pll_type = "General", clock_pll_v_altera_pll_altera_pll_i_2475.pll_vco_div = 1, clock_pll_v_altera_pll_altera_pll_i_2475.pll_vcoph_div = 1, clock_pll_v_altera_pll_altera_pll_i_2475.refclk1_frequency = "0 MHz", clock_pll_v_altera_pll_altera_pll_i_2475.reference_clock_frequency = "50.0 MHz", clock_pll_v_altera_pll_altera_pll_i_2475.sim_additional_refclk_cycles_to_lock = 0; assign locked = wire_clock_pll_v_altera_pll_altera_pll_i_2475_locked, outclk_0 = wire_clock_pll_v_altera_pll_altera_pll_i_2475_outclk[0], outclk_1 = wire_clock_pll_v_altera_pll_altera_pll_i_2475_outclk[1], outclk_2 = wire_clock_pll_v_altera_pll_altera_pll_i_2475_outclk[2], outclk_3 = wire_clock_pll_v_altera_pll_altera_pll_i_2475_outclk[3], outclk_4 = wire_clock_pll_v_altera_pll_altera_pll_i_2475_outclk[4]; endmodule //clock_pll_v //synopsys translate_on //VALID FILE