302c69937eBasic CPU design now done with afaik working hazard detection, forwarding and stalls. Tested in hardware on a EP4CE6 using two SSDisplays and dip switches to view the register content (and see if it matches the simulation). No interrupts yet as this can probably be done at a later stage.
пре 2 година
Bart
a76e895a39Started working on the CPU pipeline. Basic load, arith and jumps seem to work now. No hazard handling yet.
Bart