提交历史

作者 SHA1 备注 提交日期
  bart 28bcde6466 New SDRAM controller that uses both SDRAM chips. Now separate bus from MU for better performance, as controller runs at 100MHz. Also updated some debug code as debugging was needed. Tested working in hardware. 2x performance boost in some cases. 1 年之前
  bart 207413dd90 Assembler only needs Int: function, fixed position of program lenght. Ported ROM and UART bootloader over from FPGC5. Updated documentation on interrupts. Added resets. Fixed bug in MU. Increased stack size. Tested everything in hardware. Probably some other fixes and things I forgot. 2 年之前
  bart baff95d710 Regbank and stack are now placed in BRAM, fixed combinational loop but further testing needed. 2 年之前
  Bart 302c69937e Basic CPU design now done with afaik working hazard detection, forwarding and stalls. Tested in hardware on a EP4CE6 using two SSDisplays and dip switches to view the register content (and see if it matches the simulation). No interrupts yet as this can probably be done at a later stage. 2 年之前
  Bart e5dd555fdb Register forwarding now works for ALU operations, (memread getintid and savpc still needs forwarding). Regbank is simplified because no need for we_high anymore, load and loadhi are now done using an ALU operation. 2 年之前
  Bart 9da01544e7 Jump flush now seems to work. Made simple Quartus project to test in hardware and it seems to work fine there as well 2 年之前
  Bart a76e895a39 Started working on the CPU pipeline. Basic load, arith and jumps seem to work now. No hazard handling yet. 2 年之前
  Bart 55f619efae Initial commit with some empty Verilog template code from FPGC5 2 年之前