提交歷史

作者 SHA1 備註 提交日期
  bart 207413dd90 Assembler only needs Int: function, fixed position of program lenght. Ported ROM and UART bootloader over from FPGC5. Updated documentation on interrupts. Added resets. Fixed bug in MU. Increased stack size. Tested everything in hardware. Probably some other fixes and things I forgot. 2 年之前
  bart baff95d710 Regbank and stack are now placed in BRAM, fixed combinational loop but further testing needed. 2 年之前
  bart f5bc168700 Added DataMem to MU via Arbiter, fixed several bugs while doing this. Works with test code, but will most likely still contain bugs in certain cases. 2 年之前
  bart 0e533922fb Connected instruction memory to the MU via the arbiter 2 年之前
  bart 6881f1be1d Found bug where the next instruction after READ/WRITE is skipped if DataDelay but no InstrDelay 2 年之前
  Bart fb0e4b363f Instruction memory can now have a delay without messing up the pipeline 2 年之前
  Bart 302c69937e Basic CPU design now done with afaik working hazard detection, forwarding and stalls. Tested in hardware on a EP4CE6 using two SSDisplays and dip switches to view the register content (and see if it matches the simulation). No interrupts yet as this can probably be done at a later stage. 2 年之前
  Bart 9da01544e7 Jump flush now seems to work. Made simple Quartus project to test in hardware and it seems to work fine there as well 2 年之前
  Bart a76e895a39 Started working on the CPU pipeline. Basic load, arith and jumps seem to work now. No hazard handling yet. 2 年之前