提交历史

作者 SHA1 备注 提交日期
  bart 3af9eecaa9 Added signed fixed point multiplication to ALU. 1 年之前
  bart 01b9bb8f29 Added signed right shift operation to CPU, assembler, compiler, code and documentation. 1 年之前
  Bart e5dd555fdb Register forwarding now works for ALU operations, (memread getintid and savpc still needs forwarding). Regbank is simplified because no need for we_high anymore, load and loadhi are now done using an ALU operation. 2 年之前
  Bart a76e895a39 Started working on the CPU pipeline. Basic load, arith and jumps seem to work now. No hazard handling yet. 2 年之前
  Bart 55f619efae Initial commit with some empty Verilog template code from FPGC5 2 年之前