提交歷史

作者 SHA1 備註 提交日期
  Bart 3d9b4194f7 Added initial documentation 2 年之前
  Bart 302c69937e Basic CPU design now done with afaik working hazard detection, forwarding and stalls. Tested in hardware on a EP4CE6 using two SSDisplays and dip switches to view the register content (and see if it matches the simulation). No interrupts yet as this can probably be done at a later stage. 2 年之前
  Bart 9ec3298860 Updated README and added licence so repo can go public now 2 年之前
  Bart 9da01544e7 Jump flush now seems to work. Made simple Quartus project to test in hardware and it seems to work fine there as well 2 年之前
  Bart a76e895a39 Started working on the CPU pipeline. Basic load, arith and jumps seem to work now. No hazard handling yet. 2 年之前
  Bart 55f619efae Initial commit with some empty Verilog template code from FPGC5 2 年之前