a76905443fPorted Quartus to 5CEA5 FPGA. SDRAM does not seem to work.
1 年之前
bart
b74702c915Created full FPGC6 verilog simulation, added Quartus code from FPGC5 with CPU from FPGC6. Works in hardware, but has combination loop somewhere at the arbiter and the registerbank and stack are not using block ram
bart