提交歷史

作者 SHA1 備註 提交日期
  bart f78729ea77 Fixed L2 cache state machine issue which was only present in the previous commit. 1 年之前
  bart 82a433530c Reverted L2 cache size to 1024 words for easier debugging. 1 年之前
  bart da2bff2ea2 Removed/disabled NTSC from design, as the tiny HDMI monitor is practically always used. Also greatly increased L2 cache size, although no performance benefits for the relatively small programs I currently use for benchmarking. 1 年之前
  bart 2287e54c6b Integrated valid bits into cache block ram. Reset now iteratively clears the entire cache. Allows for much lower FPGA usage and better timings. Should be able to greatly increase cache size as there is an abundance of BRAM. 1 年之前
  bart 9a285550c0 Updated documentation a bit, added newlines to BENCH, removed wrong comments from L2cache.v 1 年之前
  bart add43b75da L2 cache at 100MHz now greatly increases performance. Attempted to create l1i and l1d cache, but becomes unstable and the issue is difficult to similate/replicate. Therefore, all l1 cache is now bypassed and the code can be found in l1cacheUnstable.v. As no l1 cache anymore, I removed some ccache statements to increase performance as this instruction currently does nothing. 1 年之前
  bart 9a6bf3cd52 Improved reset for cache. Disabled l2 cache as it currently reduces performance. Added more CCache instructions to code, although likely not needed. Still instability issues when L1I cache is enabled. 1 年之前
  bart b6831c4209 Added L2 cache (no L1 for now) between CPU and SDRAM controller. No noticable performance difference, can likely be optimized further to reduce cache hit latency. 1 年之前