 bart
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52f2819774
Removed leftover ccache instructions from debugging instability problems. Commented out required ccache instructions for when L1I cache returns in the future.
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há 1 ano atrás |
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bart
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add43b75da
L2 cache at 100MHz now greatly increases performance. Attempted to create l1i and l1d cache, but becomes unstable and the issue is difficult to similate/replicate. Therefore, all l1 cache is now bypassed and the code can be found in l1cacheUnstable.v. As no l1 cache anymore, I removed some ccache statements to increase performance as this instruction currently does nothing.
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há 1 ano atrás |
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bart
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9a6bf3cd52
Improved reset for cache. Disabled l2 cache as it currently reduces performance. Added more CCache instructions to code, although likely not needed. Still instability issues when L1I cache is enabled.
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há 1 ano atrás |
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bart
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9f74a9565f
Fixed more MU I/O bugs. Updated everything from BCC except the ASM to work on new CPU. Added back flasher programs. Fixed LOAD/HI bug by using unsigned const16 instead. Updated assembler including hotfix for FPGC jumping to addr3 after UART bootloader is done. FPGC6 now basically fully works again!
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há 2 anos atrás |
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bart
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411c20ac98
Copied over BCC from FPGC5. No modifications yet.
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há 2 anos atrás |
