 bart
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9a6bf3cd52
Improved reset for cache. Disabled l2 cache as it currently reduces performance. Added more CCache instructions to code, although likely not needed. Still instability issues when L1I cache is enabled.
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1 年間 前 |
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bart
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01b9bb8f29
Added signed right shift operation to CPU, assembler, compiler, code and documentation.
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2 年 前 |
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bart
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d55077792f
Updated BCC for B32P
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2 年 前 |
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bart
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9f74a9565f
Fixed more MU I/O bugs. Updated everything from BCC except the ASM to work on new CPU. Added back flasher programs. Fixed LOAD/HI bug by using unsigned const16 instead. Updated assembler including hotfix for FPGC jumping to addr3 after UART bootloader is done. FPGC6 now basically fully works again!
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2 年 前 |
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bart
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411c20ac98
Copied over BCC from FPGC5. No modifications yet.
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2 年 前 |
