 bart
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52f2819774
Removed leftover ccache instructions from debugging instability problems. Commented out required ccache instructions for when L1I cache returns in the future.
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1 年間 前 |
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bart
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add43b75da
L2 cache at 100MHz now greatly increases performance. Attempted to create l1i and l1d cache, but becomes unstable and the issue is difficult to similate/replicate. Therefore, all l1 cache is now bypassed and the code can be found in l1cacheUnstable.v. As no l1 cache anymore, I removed some ccache statements to increase performance as this instruction currently does nothing.
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1 年間 前 |
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bart
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5af536210d
Fixed instability by adding clear cache instruction during SPI transfer. No idea why this fixed the issue, as the I/O address range is above the limit for cache to work.
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1 年間 前 |
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bart
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01b9bb8f29
Added signed right shift operation to CPU, assembler, compiler, code and documentation.
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2 年 前 |
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bart
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411c20ac98
Copied over BCC from FPGC5. No modifications yet.
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2 年 前 |
